CODELOADER
디바이스 레지스터 프로그래밍용 CodeLoader 소프트웨어
CODELOADER
개요
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | Loop filter & device configuration + simulation | Device register programming |
LMX24xx PLL family | EasyPLL | CodeLoader* |
LMX25xx PLL+VCO family | ||
LMK jitter cleaners and distributors |
*For new designs, use the Clocks and Synthesizers (TICS) Pro Software tool.
다운로드
소프트웨어 프로그래밍 도구
The design resource accessed as www.ti.com/lit/zip/snac014 or www.ti.com/lit/xx/snac014e/snac014e.zip has been migrated to a new user experience at www.ti.com/tool/download/SNAC014. Please update any bookmarks accordingly.
필요할 수 있는 추가 리소스
설계 툴
PLLATINUMSIM-SW — PLLatinum Sim Tool
지원되는 제품 및 하드웨어
제품
IQ 복조기
RF PLL 및 신시사이저
클록 네트워크 싱크로나이저
클록 버퍼
클록 생성기
클록 지터 클리너
하드웨어 개발
평가 보드
PLLATINUMSIM-SW — PLLatinum Sim Tool
제품
IQ 복조기
RF PLL 및 신시사이저
클록 네트워크 싱크로나이저
클록 버퍼
클록 생성기
클록 지터 클리너
하드웨어 개발
평가 보드
출시 정보
Bug fixes
새 소식
- Fixed Kvco calculation bug introduced in 1.6.6
- Added warning for loop bandwidth being restricted due to min high order capacitance.
지원 소프트웨어
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
지원되는 제품 및 하드웨어
제품
RF PLL 및 신시사이저
오실레이터
클록 네트워크 싱크로나이저
클록 버퍼
클록 생성기
클록 지터 클리너
하드웨어 개발
평가 보드
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.8.0 installer binary for Windows operating system
제품
RF PLL 및 신시사이저
오실레이터
클록 네트워크 싱크로나이저
클록 버퍼
클록 생성기
클록 지터 클리너
하드웨어 개발
평가 보드
문서
TICS Pro 1.7.8.0 Software Manifest
TICS Pro 1.7.8.0 Release Notes
출시 정보
Added
- LMK5C23208A
Improvements
- TCP server returns error descriptions
- TICSPro_TCP.py updated for python ≥ 3.10. Remove type annotations if backward compatibility with older python versions is required.
- LMK5B/5C:
- Warn when GPIOx selects REFx monitor, but REFx is not programmed
- Relative calculation of DPLLx_PH_OFFSET value
- Added fields and improved frequency planning for 1-PPS outputs
- PLLx_RDIV_MUX_SEL only sets recommended values when dropdown is changed; no longer changed by DPLL loop filter calculation or TCS file load
- Advanced Options checkbox added on Getting Started page
- GPIOx descriptions updated for accuracy
- LMK5B12212, LMK5C12212A:
- New step added to Start Page process to reduce current consumption and noise
- SRAM sequence EEPROM generation sets optimized values from new step in Start Page process
- LMK5B33414, LMK5C33414A:
- Simplified programming sequence by combining writes for the output divider synchronization sequence generator
Bug Fixes
- LMK5B12212, LMK5C12212A:
- Some controls which were not register-backed have been updated to be register-backed.
- LMK5B33414, LMK5C33414A:
- Fixed "Set SYNC Enable" buttons on "SYNC/SYSREF/1-PPS" page
Known Issues
- LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
기술 자료
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