SBAA275A June   2018  – March 2023 ADS1120 , ADS112C04 , ADS112U04 , ADS1147 , ADS1148 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1220 , ADS122C04 , ADS122U04 , ADS1247 , ADS1248 , ADS124S06 , ADS124S08 , ADS125H02 , ADS1260 , ADS1261 , ADS1262 , ADS1263

 

  1.   A Basic Guide to RTD Measurements
  2. 1RTD Overview
    1. 1.1 Callendar-Van Dusen Equation
    2. 1.2 RTD Tolerance Standards
    3. 1.3 RTD Wiring Configurations
    4. 1.4 Ratiometric Measurements
      1. 1.4.1 Lead Resistance Cancellation
      2. 1.4.2 IDAC Current Chopping
    5. 1.5 Design Considerations
      1. 1.5.1 Identify the RTD Range of Operation
      2. 1.5.2 Set the Excitation Current Sources and Consider RTD Self Heating
      3. 1.5.3 Set Reference Voltage and PGA Gain
      4. 1.5.4 Verify the Design Fits the Device Range of Operation
      5. 1.5.5 Design Iteration
  3. 2RTD Measurement Circuits
    1. 2.1  Two-Wire RTD Measurement With Low-Side Reference
      1. 2.1.1 Schematic
      2. 2.1.2 Pros and Cons
      3. 2.1.3 Design Notes
      4. 2.1.4 Measurement Conversion
      5. 2.1.5 Generic Register Settings
    2. 2.2  Two-Wire RTD Measurement With High-Side Reference
      1. 2.2.1 Schematic
      2. 2.2.2 Pros and Cons
      3. 2.2.3 Design Notes
      4. 2.2.4 Measurement Conversion
      5. 2.2.5 Generic Register Settings
    3. 2.3  Three-Wire RTD Measurement, Low-Side Reference
      1. 2.3.1 Schematic
      2. 2.3.2 Pros and Cons
      3. 2.3.3 Design Notes
      4. 2.3.4 Measurement Conversion
      5. 2.3.5 Generic Register Settings
      6. 2.3.6 Chopping IDAC Currents for Matching
    4. 2.4  Three-Wire RTD Measurement, Low-Side Reference, One IDAC Current Source
      1. 2.4.1 Schematic
      2. 2.4.2 Pros and Cons
      3. 2.4.3 Design Notes
      4. 2.4.4 Measurement Conversion
      5. 2.4.5 Configuration Register Settings
    5. 2.5  Three-Wire RTD Measurement, High-Side Reference
      1. 2.5.1 Schematic
      2. 2.5.2 Pros and Cons
      3. 2.5.3 Design Notes
      4. 2.5.4 Measurement Conversion
      5. 2.5.5 Configuration Register Settings
    6. 2.6  Four-Wire RTD Measurement, Low-Side Reference
      1. 2.6.1 Schematic
      2. 2.6.2 Pros and Cons
      3. 2.6.3 Design Notes
      4. 2.6.4 Measurement Conversion
      5. 2.6.5 Configuration Register Settings
    7. 2.7  Two Series Two-Wire RTD Measurements, Low-Side Reference
      1. 2.7.1 Schematic
      2. 2.7.2 Pros and Cons
      3. 2.7.3 Design Notes
      4. 2.7.4 Measurement Conversion
      5. 2.7.5 Configuration Register Settings
    8. 2.8  Two Series Four-Wire RTD Measurements
      1. 2.8.1 Schematic
      2. 2.8.2 Pros and Cons
      3. 2.8.3 Design Notes
      4. 2.8.4 Measurement Conversion
      5. 2.8.5 Configuration Measurement Settings
    9. 2.9  Multiple Two-Wire RTD Measurements
      1. 2.9.1 Schematic
      2. 2.9.2 Pros and Cons
      3. 2.9.3 Design Notes
      4. 2.9.4 Measurement Conversion
      5. 2.9.5 Configuration Register Settings
    10. 2.10 Multiple Three-Wire RTD Measurements
      1. 2.10.1 Schematic
      2. 2.10.2 Pros and Cons
      3. 2.10.3 Design Notes
      4. 2.10.4 Measurement Conversion
      5. 2.10.5 Configuration Register Settings
    11. 2.11 Multiple Four-Wire RTD Measurements in Parallel
      1. 2.11.1 Schematic
      2. 2.11.2 Pros and Cons
      3. 2.11.3 Design Notes
      4. 2.11.4 Measurement Conversion
      5. 2.11.5 Configuration Register Settings
    12. 2.12 Universal RTD Measurement Interface With Low-Side Reference
      1. 2.12.1 Schematic
      2. 2.12.2 Pros and Cons
      3. 2.12.3 Design Notes
        1. 2.12.3.1 Universal Measurement Interface - Two-Wire RTD
        2. 2.12.3.2 Universal Measurement Interface - Three-Wire RTD
        3. 2.12.3.3 Universal Measurement Interface - Four-Wire RTD
      4. 2.12.4 Measurement Conversion
        1. 2.12.4.1 Two-Wire Measurement
        2. 2.12.4.2 Three-Wire Measurement
        3. 2.12.4.3 Four-Wire Measurement
      5. 2.12.5 Configuration Register Settings
    13. 2.13 Universal RTD Measurement Interface With High-Side Reference
      1. 2.13.1 Schematic
      2. 2.13.2 Pros and Cons
      3. 2.13.3 Design Notes
        1. 2.13.3.1 Universal Measurement Interface, High-Side Reference - Two-Wire RTD
        2. 2.13.3.2 Universal Measurement Interface, High-Side Reference - Three-Wire RTD
        3. 2.13.3.3 Universal Measurement Interface, High-Side Reference - Four-Wire RTD
      4. 2.13.4 Measurement Conversion
        1. 2.13.4.1 Two-Wire Measurement
        2. 2.13.4.2 Three-Wire Measurement
        3. 2.13.4.3 Four-Wire Measurement
      5. 2.13.5 Configuration Register Settings
  4. 3Summary
  5. 4Revision History

2.3.3 Design Notes

For this three-wire RTD design, two matched IDAC current sources are used to actively cancel the lead resistance errors. IDAC1 sources current through lead 1 of the RTD to both the RTD and the reference resistor, RREF. IDAC2 sources current through lead 2 of the RTD to the reference resistor. If IDAC1 and IDAC2 are identical and the lead resistances match, then the error from the lead resistances cancels in the measurement made from AIN1 and AIN2.

The measurement circuit requires:

  • Two dedicated IDAC output pins
  • AINP and AINN inputs
  • External reference input
  • Precision reference resistor

Note that the RTD is driven from IDAC1 while RREF is driven by IDAC1 and IDAC2 combined. Presuming that the IDAC currents match, the measurement is also ratiometric, and does not require converting the input or reference to voltage for the conversion. As with the two-wire RTD measurement, the topology requires a precision reference resistor with high accuracy and low drift.

IDAC currents from AIN0 and AIN3 are driven into two of the three RTD leads. IDAC1 drives the RTD and one lead resistance, while IDAC2 drives the second lead resistance. The voltage drop across the lead resistances cancel each other in the ADC measurement, assuming the IDAC currents match and the lead resistances match. Without the lead resistances, the measurement voltage is IIDAC1 • RRTD, while the reference voltage is (IIDAC1 + IIDAC2) • RREF. If the two IDAC currents match, the IDAC terms drop out of the measurement conversion.

The following shows how the matched IDAC sources cancel the lead resistance errors. Equation 24 and Equation 25 start with the voltages at AIN1 and AIN2 and include the lead resistance contribution.

Equation 24. VAIN1 = [IIDAC1 • (RRTD + RLEAD1)] + [(IIDAC1 + IIDAC2) • (RLEAD3 + RREF)]
Equation 25. VAIN2 = (IIDAC2 • RLEAD2) + [(IIDAC1 + IIDAC2) • (RLEAD3 + RREF)]

The ADC input voltage measures VAIN1 – VAIN2, with RLEAD3 and RREF terms dropping out.

Equation 26. VAIN1 − VAIN2 = [IIDAC1 • (RRTD + RLEAD1)] − (IIDAC2 • RLEAD2)

Assuming the lead resistances are equal and the IDAC currents are matched, so that RLEAD1 = RLEAD2 = RLEAD and IIDAC1 = IIDAC2 = IIDAC. The result becomes:

Equation 27. VAIN1 − VAIN2 = IIDAC • RRTD

At the same time, the reference resistor shunts the sum of IIDAC1 and IIDAC2 to become:

Equation 28. VREF = (IIDAC1 + IIDAC2) • RREF = 2 • IIDAC • RREF

As with the two wire RTD example, start the design with the expected usable range of the RTD. The reference resistor and IDAC current values are chosen to place the input voltage within the PGA range, while ensuring that the IDAC is operating within its compliance voltage. As in all ratiometric measurements, the reference resistor, RREF must be a precision resistor with high accuracy and low drift.

To verify that the design is within the ADC range of operation, start by calculating the voltages of AIN1 and AIN2 and the maximum differential input voltage. Assuming the lead resistances are small and can be ignored, Equation 24 and Equation 25 reduce to Equation 29 and Equation 30. Verify that VAIN1 and VAIN2 are within the input range of the PGA given the gain setting and supply voltage. Use the maximum RTD resistance based on the desired temperature measurement.

Equation 29. VAIN1 = (IIDAC1 • RRTD) + (IIDAC1 + IIDAC2) • RREF
Equation 30. VAIN2 = (IIDAC1 + IIDAC2) • RREF

Additionally, verify the output voltage of the IDAC sources calculated from VAIN0 and VAIN3 are low enough from AVDD to be within the compliance voltage of the IDAC current source. Because the voltage for IDAC1 always be higher than that of IDAC2, it is sufficient to calculate the output voltage at VAIN0 to verify the IDAC compliance voltage. This calculation is already shown in Equation 29, because VAIN0 is the same potential as VAIN1.

The reference resistor, RREF must be a precision resistor with high accuracy and low drift. Any error in the RREF reflects the same error in the RTD measurement. The REFP0 and REFN0 pins are shown connecting to the RREF resistor as a Kelvin connection to get the best measurement of the reference voltage. This eliminates any series resistance as an error from the reference resistance measurement.