1.3 Mitigating Latch-Up

There are methods employed to reduce the possible onset of Latch-Up. Spacing of the elements of each transistor, diode, resistor and capacitor are now being controlled through process characterization and design rules to help minimize the effect of current or voltage pulses on the products. Additionally, guard rings have been added around known radiators in the circuits or if spacing concerns are critical around individual PMOS and NMOS transistors, diodes or substrate resistors. Guard rings act as injected carrier syphons allowing these carriers to flow to the supply or ground. Also, the use of substrate ties and well taps act as excited carrier syphons and are guided by design rules for placement. These ties and taps are necessary for Latch-Up immunity. Another very effective method of quenching Latch-Up is to use an EPI (epitaxial silicon) layer. The EPI layer is doped appropriately for the best transistor performance (more lightly doped than the remaining lower portion of the substrate that is highly doped). The highly doped substrate directs majority carriers to ground and reflects minority carriers making the guard rings more effective (see Figure 3). Even with these safeguards, there is a possibility of parasitic transistors in circuits that are not identified. These unidentified Latch-Up sources need to be identified; one way is a Latch-Up stress test.