SLAAEG6A November   2023  – September 2024 TAA5212 , TAA5242 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5142 , TAC5211 , TAC5212 , TAC5212-Q1 , TAC5242 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5142 , TAD5212 , TAD5212-Q1 , TAD5242

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Operating Modes for the Clocking
    1. 2.1 Automatic Modes of Operation
  6. 3Clocking Modes
    1. 3.1 Auto Primary BCLK Ratio
    2. 3.2 Auto Secondary BCLK Ratio
    3. 3.3 Auto MCLK Ratio
    4. 3.4 Auto MCLK Fixed
    5. 3.5 Custom Mode and Semi Automatic Mode of Operation
      1. 3.5.1 Semi-Automatic Mode
    6. 3.6 Additional Clocks
      1. 3.6.1 PDM Clocks
      2. 3.6.2 Boost Clock
      3. 3.6.3 SAR Clock
      4. 3.6.4 CLKOUT
  7. 4Clocking in Hardware Controlled Devices
  8. 5Revision History

4 Clocking in Hardware Controlled Devices

The Tax5x1x family also has some Hardware pin controlled Variants.

TAA5242 is the ADC Variant. TAD5142 and TAD5242 are the DAC variants.

The hardware variants support an Audio Bus Controller ot target mode of operation using Mode pin MD0. In target mode ,FSYNC and BCLK work as input pins. In controller mode FSYNC and BCLK work as output pins. This is indicated in the table below.

The Hardware device supports automatic clocking as shown in Section 2.1.

Table 4-1 Controller and Target Mode Selection
MD0 Controller and Target Selection
Short to ground Target I2S mode
Short to ground with 4.7KΩ Target TDM mode
Short to AVDD Controller I2S module
Short to AVDD with 4.7KΩ Controller TDM mode
Short to AVDD with 22K Ω Target LJ mode