Clocking Configuration of Device and Flexible Clocking For TAx5x1x Family

Abstract

This document applies to the following part numbers:

TAC5212, TAC5112, TAC5211, TAC5111, TAA5212, TAD5212, TAD5112, TAC5412-Q1, TAC5411-Q1, TAC5312-Q1, TAC5311-Q1, TAC5212-Q1, TAC5211-Q1, TAC5112-Q1, TAC5111-Q1, TAA5412-Q1, TAD5212-Q1, TAD5112-Q1,TAA5242,TAD5142,TAD5242

These devices have a smart auto-configuration block to generate all necessary internal clocks required for the ADC and DAC Circuitry as well as the digital filter engine used for signal processing. This configuration is done by monitoring the frequency of the FSYNC and BCLK signal on the audio buses. The device supports the various data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming.

Trademarks

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1 Introduction

The Device Supports a Primary as well as Secondary ASI. There are several automatic modes of operation described where either the primary BCLK /FYSNC or Secondary BCLK/FSYNC can be used for determination of the incoming timing modes.

In addition, the MCLK / FSYNC can also be used to do the timing determination.

The device has the following interfaces that setup the clocking.

Interface	Setup
MCLK	Master Clock
FSYNC	Primary FSYNC/ Secondary SYNC
PASI BCLK	Primary BCLK
PASI FSYNC	Primary FSYNC
SASI BCLK	Secondary BCLK
SASI FSYNC	Secondary SYNC

The BCLK and FSYNC Pins as well as the GPIO/GPI/GPO pins can be configured to setup the Primary and Secondary ASI.

The timings must lie within the limits described in Table 1-1 and Table 1-2.

Table 1-1 Multiples of 48Khz

Pins	Timings
Fs	3KHz-768KHz
BCLK	256KHz - 24.576MHz
MCLK	256KHz - 49.152MHz

Table 1-2 Multiples of 44.1Khz

Pins	Timings
Fs	2.75KHz-705.6KHz
BCLK	235.2KHz – 22.57MHz
MCLK	235.1KHz - 45.15MHz

Note: The nomenclature of Target is used to indicate Slave Mode of Operation. The nomenclature of Controller is used to indicate Master Mode of operation.