SLAAEG6A November   2023  – September 2024 TAA5212 , TAA5242 , TAA5412-Q1 , TAC5111 , TAC5111-Q1 , TAC5112 , TAC5112-Q1 , TAC5142 , TAC5211 , TAC5212 , TAC5212-Q1 , TAC5242 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5112 , TAD5112-Q1 , TAD5142 , TAD5212 , TAD5212-Q1 , TAD5242

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Operating Modes for the Clocking
    1. 2.1 Automatic Modes of Operation
  6. 3Clocking Modes
    1. 3.1 Auto Primary BCLK Ratio
    2. 3.2 Auto Secondary BCLK Ratio
    3. 3.3 Auto MCLK Ratio
    4. 3.4 Auto MCLK Fixed
    5. 3.5 Custom Mode and Semi Automatic Mode of Operation
      1. 3.5.1 Semi-Automatic Mode
    6. 3.6 Additional Clocks
      1. 3.6.1 PDM Clocks
      2. 3.6.2 Boost Clock
      3. 3.6.3 SAR Clock
      4. 3.6.4 CLKOUT
  7. 4Clocking in Hardware Controlled Devices
  8. 5Revision History

2.1 Automatic Modes of Operation

The Fsync and BCLK-to-Fsync-Ratio of the Primary ASI Interface are auto detected by the device. Based on the device configuration (number of channels, signal processing configuration, and so on), all clock dividers/mux selects are auto inferred.

PLL enablement is auto Inferred based upon the MIPS Required and highest Clock Frequency available in the system.

Table 2-1 shows the different sample rates that are recognized by the automatic configuration module. Incoming timings are split into several buckets of frequency. Note that for automatic modes the incoming FSYNC must be within one of the frequency buckets

Table 2-1 Sample Rates Accepted in the Automatic Mode
Fs Min (KHz) Fs Typ (KHz) Fs Max (KHz)
698.54 768 775.68
349.27 384 387.84
174.64 192 193.92
87.32 96 96.96
43.66 48 48.48
29.11 32 32.32
21.83 24 24.24
14.55 16 16.16
10.91 12 12.12
7.28 8 8.08
4.37 4.8 4.85
2.73 3 3.03

Table 2-2 shows the BCLK to FSYNC Ratios that are recognized by the automatic clocking mechanism.

Table 2-2 BCLK to FSYNC Ratio
Expanded List of BCLK to Fs Ratio Supported
16 20 24 32 40 48 60 64 72 80 96
100 112 120 128 140 144 160 168 176 180 192
200 208 216 220 224 240 256 260 264 272 280
288 300 304 312 320 336 340 352 360 368 380
384 400 408 416 420 432 440 448 456 460 464
480 496 500 504 512 520 528 540 544 552 560
576 580 592 600 608 620 624 640 648 656 660
672 680 688 696 700 704 720 736 740 744 752
760 768 780 784 792 800 816 820 832 840 848
860 864 880 888 896 900 912 920 928 936 940
944 960 976 980 984 992 1000 1008 1020 1024 1032
1040 1056 1060 1080 1088 1100 1104 1120 1128 1140 1152
1160 1176 1180 1184 1200 1216 1220 1224 1240 1248 1260
1272 1280 1296 1312 1320 1344 1368 1376 1392 1408 1416
1440 1464 1472 1488 1504 1512 1536 1568 1600 1632 1664
1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016
2048
Note: In Automatic clocking the device recognizes integer ratios of BCLK/FSYNC. However, Table 2-2 shows some ratios of BCLK/FSYNC where optimum SNR and lowest power consumption is obtained. Therefore, these timings are preferred.

Refer to the Table 2-1 and Table 2-2 above. If the incoming frequency is 43.66Mhz and the Incoming BCLK is 873.2Khz then the automatic configuration shall recognize the BCLK/Fs ratio as 20 and shall setup the internal clocking accordingly.