Figure 1-1 and Figure 1-2 illustrate the functional block diagrams for TI's 25G/28G retimers and redrivers. As evident from the block diagrams, the retimer and redriver have a few key functional differences.

• The retimer implements clock and data recovery (CDR) and sampler functional blocks, thus enabling it to output a retimed version of the input signal with lower jitter. The redriver on the other hand does not incorporate the retiming-CDR related functional blocks.
• The redriver implements a two-stage continuous time linear equalizer (CTLE) as its only form of receive equalization.
• In addition to CTLE, the retimer also implements a decision feedback equalizer (DFE). Thus the retimer is equipped with more enhanced post-cursor equalization function.
• The retimer incorporates additional diagnostic functions not available on the redriver, including PRBS pattern generation and checking and eye monitor functions.

Figure 1-1 DS280DF810 Retimer Functional Block Diagram

Figure 1-2 DS280MB810 Redriver Functional Block Diagram

Table 2-1 lists a high-level summary of chip-to-chip interface types based on their transmission channel's insertion loss at around the Nyquist frequency for 25Gbps data rate. The amount of channel loss will dictate the level of signal conditioning required for an error free chip-to-chip link. Some portion of system interconnects will have channel loss that is within the equalization compensation capability of the chips being linked together. Such links do not require signal conditioning. Links requiring a moderate amount of compensation (up to 20dB) may use a redriver instead of a retimer, in that way realizing some relative savings in power consumption and cost. Links involving transmission across a channel with very high loss require the use of a retimer.

Referring back to Section 5, TI's 25G/28G retimer part numbers cover slightly different but over-lapping data rates, as each is targeted for specific sets of high-speed interface applications as part of a networking system. Table 3-1 lists the most common high-speed networking interface standards utilizing TI retimers along with recommendations on the most appropriate TI retimer part numbers.

Link training is an optional Physical Coding Sublayer (PCS) function specified by the IEEE 802.3 Ethernet specification. It is also used by other standards such as PCIe and Fibre Channel. Link training is a state-machine based algorithm that enables two interconnected systems to converge on their respective optimal transmit equalization settings. Typically the switch ASIC (either front-port or backplane) implements the link training function. Signal conditioners such as TI retimers and redrivers are by definition mid-channel devices. In other words, these devices are placed in the middle of the ASIC-to-ASIC link to provide channel reach extension. The level of link training support offered by signal conditioners can be broken down into three categories, as described in Table 4-1.

• Recommendation: 25G system developers requiring Link Training support may implement TI's 25G/28G redrivers for mid-channel reach extension.