SPNA239 September   2019 RM46L440 , RM46L450 , RM46L830 , RM46L840 , RM46L850 , RM46L852 , RM48L530 , RM48L540 , RM48L730 , RM48L740 , RM48L940 , RM48L950 , RM48L952 , RM57L843 , TMS570LC4357 , TMS570LC4357-EP , TMS570LC4357-SEP , TMS570LS0232 , TMS570LS0332 , TMS570LS0432 , TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS1114 , TMS570LS1115 , TMS570LS1224 , TMS570LS1225 , TMS570LS1227 , TMS570LS20206 , TMS570LS20206-EP , TMS570LS20216 , TMS570LS20216-EP , TMS570LS2124 , TMS570LS2125 , TMS570LS2134 , TMS570LS2135 , TMS570LS3134 , TMS570LS3135 , TMS570LS3137 , TMS570LS3137-EP

 

  1.   HALCoGen Ethernet Driver With lwIP Integration Demo and Active Web Server Demo
    1.     Trademarks
    2. 1 Introduction
    3. 2 Supported Features
    4. 3 Get the Software
    5. 4 Configuring EMAC and MDIO Using HALCoGen GUI for the lwIP Demo
      1. 4.1 RM46x, RM48x and TMS570LSx HDK
      2. 4.2 TMS570LC43x and RM57x HDK
      3. 4.3 RM57x Launchpad (LAUNCHXL2 RM57x)
      4. 4.4 TMS570LC43 Launchpad (LAUNCHXL2 570LC43x)
    6. 5 Additional Changes for Active Web Server Demo
      1. 5.1 HALCoGen Configuration Changes
      2. 5.2 lwIP Port Changes
      3. 5.3 CCS Project Structure
      4. 5.4 Changing the Web Pages Rendered by Web Server
    7. 6 Programming Sequence Using HALCoGen Generated Drivers
    8. 7 Design of lwIP Integration
      1. 7.1 Hardware Abstraction Layer
      2. 7.2 lwIP Interface Layer
      3. 7.3 Hercules Development Network Interface Layer
        1. 7.3.1 Network Device Initialization
        2. 7.3.2 Packet Data Transmission
        3. 7.3.3 Packet Data Reception
      4. 7.4 lwIP Application Layer
      5. 7.5 System Application Layer
    9. 8 Release Folder Structure
    10. 9 Run the Test
      1. 9.1 Hardware Setup
      2. 9.2 Building and Executing the lwIP Demo
      3. 9.3 Building and Executing the Active Web Server Demo
        1. 9.3.1 I/O Control Demo 1
        2. 9.3.2 I/O Control Demo 2

6 Programming Sequence Using HALCoGen Generated Drivers

Using the HALCoGen generated driver code (through the procedure above), the following sequence can be used to configure and operate the EMAC and MDIO modules.

  1. Initialize the EMAC module by calling EMACInit(). This API resets the EMAC and EMAC Control Module Registers.
  2. Initialize the MDIO Module using MDIOInit(). Insert a short delay after this function returns to ensure that MDIO module initialization completes successfully before using other MDIO APIs.
  3. Auto-negotiate with the PHY device connected to MDIO. PHY Auto negotiation APIs are provided as reference and must be adapted to the external PHY present on the hardware.
  4. After completing auto negotiation, get the auto negotiation result using the respective PHY’s link partner ability API and set the duplex mode of operation in the EMAC using EMACDuplexSet().
  5. Set the MAC Address in the EMAC hardware using EMACMACAddrSet().
  6. Enable unicast for a specific channel using the EMACRxUnicastSet() API (optional).
  7. Initialize the TX and RX buffer descriptors in the CPPI RAM, which is local to the EMAC.
  8. Enable the TX operation in EMAC using EMACTxEnable(). This enables the EMAC hardware transmit operation. However, transmission will not start until a valid descriptor pointer is written using EMACTxHdrDescPtrWrite().
  9. Enable the RX operation in EMAC using EMACRXEnable().
  10. Write the RX Header Descriptor Pointer using EMACRxHdrDescPtrWrite(). The EMAC hardware will start receiving data at this point. The data is stored to the buffer pointer in this buffer descriptor. After the buffer corresponding to this descriptor is filled, the next descriptor is used by the EMAC hardware according to the buffer descriptor settings.
  11. Enable MII using EMACMIIEnable().
  12. Enable the Transmit and Receive Pulse interrupts using EMACTxIntPulseEnable() and EMACRxIntPulseEnable(). The interrupts will be routed through the EMAC Control Core to the CPU interrupt controller. This enables the EMAC TX and RX pulse interrupts at EMAC peripheral level only. The core interrupts must be enabled separately in the VIM.

The following guidelines should be observed when writing an EMAC interrupt service routine (ISR):

  • In an EMAC Transmit ISR, the interrupt must be acknowledged to the EMAC hardware using EMACCoreIntAck(). However, the interrupt will be cleared only if the completion pointer is written using the EMACTxCPWrite() API with the last processed TX buffer descriptor.
  • In an EMAC Receive ISR, the interrupt must be acknowledged to the EMAC hardware using EMACCoreIntAck(). Again, the interrupt will be cleared only if the completion pointer is written using the EMACRxCPWrite() API with the last processed RX buffer descriptor.