The Sitara MCU family is an Arm-based architecture which incorporates ASIL-D functional safety, Evita-full Hardware Security Module (HSM), and AUTOSAR support in addition to real-time control capabilities. The Arm Cortex-R5F cluster in the Sitara MCU family includes up to 4-cores. Surrounding the core are accompanying memories such as L1 cache and tightly-coupled memories (TCM), standard Arm CoreSight™ debug and trace architecture, integrated vectored interrupt manager (VIM), ECC aggregators, and various other modules. The accelerator for real-time control inherits the classic C2000 control modules. The accelerator includes: analog-to-digital converter (ADC), analog comparator, buffered digital-to-analog converter, enhanced pulse width modulator (EPWM), enhanced capture, enhanced quadrature encoder pulse, fast serial interface, sigma delta filter module, and crossbar. Other benefits include: Flexible lockstep options for split safety decomposition, Hardware Security Module (HSM), CAN-FD support with AUTOSAR. A Traction inverter system block diagram controlled by AM2634-Q1 is shown in #FIG_GCM_5CZ_N5B.

The Code Composer Studio™ software project folder includes traction inverter demonstration codes. The resolver loop is implemented as follows: one PWM channel is set to trigger updates for a resolver excitation signal through direct memory access and a digital-to-analog converter (DAC) at higher frequencies, while three other PWM channels create an inverter signal and generate an ADC SOC. The resolver excitation signal is aligned from the DAC to the desired phase for ADC samples. Multiple ADC units can share the same System on Chip (SOC).