SLUAAE9B May 2022 – November 2023 TPS62860 , TPS62861 , TPS62864 , TPS62866 , TPS62868 , TPS62869 , TPS62870 , TPS62870-Q1 , TPS62871 , TPS62871-Q1 , TPS62872 , TPS62872-Q1 , TPS62873 , TPS62873-Q1 , TPS62874-Q1 , TPS62875-Q1 , TPS62876-Q1 , TPS62877-Q1 , TPS6287B10 , TPS6287B15 , TPS6287B20 , TPS6287B25 , TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15
With increasing needs to compute data fast in a reliable way, DC-DC converters continue to see lower output voltages and even stricter core rail supply AC and DC regulation specifications. To be able to provide significant amount of current in a very short time window, features like droop compensation helps to reduce over shoot and undershoot of the core voltage during load variation.
Some power rail like SoC and FPGA core rails have strict load requirement. By enabling the droop compensation setting via I2C, TPS62876-Q1/TPS6287B25 helps to increase the voltage margin on a supply rail, inherently allowing a reduction of the output capacitance needed to achieve a defined load transient peak to peak target. Figure 6-1 shows a comparison for a quick load change.
Droop disabled | Droop enabled |
---|---|
76.85 mV | 58.74 mV |
About 25% improvement can be observed on that specific case. By nature of the droop compensation feature implementation, best-case to use this feature is for a fast load change from 10 to 90% of output current rating.