When using the RGMII interface mode, timing issues related to clock delay with respect to data can be determined by using a method of lowering the maximum bit rate allowed for the Ethernet link. This limit can be done with three methods:

1. Use ethtool to manually set the link speed on both link partners:
   ethtool -s <interface name> speed <link speed>
2. Connect to a lower bit rate link partner
3. Add a max-speed property to the DTS to lower the bit rate. This method is preferred as this is set on each DUT during boot time. The following code snippet shows an example of adding this property to the PHY node in a DTS file. Observe that the speed is set to the lowest setting of 10 indicating 10Mbps. 100Mbps can also work. A default speed of 1000Mbps from the PHY HW configuration is assumed here.

cpsw3g_phy1: ethernet-phy1@ {
   …
   max-speed = <10>;
   …
};