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SN74SSTVF16857

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14-bit registered buffer with SSTL_2 inputs and outputs

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Data sheet

SN74SSTVF16857

ACTIVE
Data sheet Order now

Product details

Function Memory interface Output frequency (max) (MHz) 250 Number of outputs 14 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Features DDR register Operating temperature range (°C) 0 to 70 Rating Catalog Output type SSTL-18 Input type SSTL-18
Function Memory interface Output frequency (max) (MHz) 250 Number of outputs 14 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Features DDR register Operating temperature range (°C) 0 to 70 Rating Catalog Output type SSTL-18 Input type SSTL-18
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200
  • Pinout and Functionality Compatible With JEDEC Standard SSTV16857
  • 600 ps Faster (Simultaneous Switching) Than JEDEC Standard SSTV16857 in PC2700 DIMM Applications
  • Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated DIMM Load
  • Outputs Meet SSTL_2 Class I Specifications
  • Supports SSTL_2 Data Inputs
  • Differential Clock (CLK and CLK\) Inputs
  • Supports LVCMOS Switching Levels on the RESET\ Input
  • RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200
  • Pinout and Functionality Compatible With JEDEC Standard SSTV16857
  • 600 ps Faster (Simultaneous Switching) Than JEDEC Standard SSTV16857 in PC2700 DIMM Applications
  • Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated DIMM Load
  • Outputs Meet SSTL_2 Class I Specifications
  • Supports SSTL_2 Data Inputs
  • Differential Clock (CLK and CLK\) Inputs
  • Supports LVCMOS Switching Levels on the RESET\ Input
  • RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.

The SN74SSTVF16857 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.

This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.

The SN74SSTVF16857 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.
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Technical documentation

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Type Title Date
* Data sheet SN74SSTVF16857 datasheet (Rev. B) 03 Apr 2003
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note 56-Pin Quad Flatpack No-Lead Logic Package 07 Feb 2003
Application note Application of the SN74SSTVF16857 in Planar PC2700 (DDR-333) RDIMMs 10 Jan 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature DIMM Module Solution 13 Jun 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note Application of the SN74SSTV32852 in Stacked, Low-Profile (1U) PC-1600/2100 DIMMs 07 Nov 2001
Application note Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859 09 Feb 2001

Design & development

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Simulation model

HSPICE Model of SN74SSTVF16857

SCEJ141.ZIP (45 KB) - HSpice Model
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Simulation model

SN74SSTVF16857 IBIS Model

SCEM271.ZIP (17 KB) - IBIS Model
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