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CD74AC02

ACTIVE

4-ch, 2-input, 1.5-V to 5.5-V NOR gates

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Data sheet

CD74AC02

ACTIVE
Data sheet Order now

Product details

Technology family AC Number of channels 4 Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Inputs per channel 2 IOL (max) (mA) 24 IOH (max) (mA) -24 Output type Push-Pull Input type Standard CMOS Features Standard speed (tpd > 50ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -55 to 125
Technology family AC Number of channels 4 Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Inputs per channel 2 IOL (max) (mA) 24 IOH (max) (mA) -24 Output type Push-Pull Input type Standard CMOS Features Standard speed (tpd > 50ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -55 to 125
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6
  • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Balanced propagation delays

  • ±24mA output drive current

    – Fanout to 15 F devices

  • SCR-latchup-resistant CMOS process and circuit design
  • Exceeds 2kV ESD protection per MIL-STD-883, method 3015
  • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Balanced propagation delays

  • ±24mA output drive current

    – Fanout to 15 F devices

  • SCR-latchup-resistant CMOS process and circuit design
  • Exceeds 2kV ESD protection per MIL-STD-883, method 3015

The ’AC02 devices contain four independent 2-input NOR gates that perform the Boolean function Y = A•B or Y = A + B in positive logic.

The ’AC02 devices contain four independent 2-input NOR gates that perform the Boolean function Y = A•B or Y = A + B in positive logic.
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Technical documentation

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Type Title Date
* Data sheet CDx4AC02 Quadruple 2-Input Positive-nor Gates datasheet (Rev. D) PDF | HTML 25 Jul 2024
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
More literature HiRel Unitrode Power Management Brochure 07 Jul 2009
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

CD74AC02 Behavioral SPICE Model

SCHM034.ZIP (7 KB) - PSpice Model
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Package Pins CAD symbols, footprints & 3D models
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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