DM383

• High-Performance DaVinci Digital Media Processors
  • Up to 1000-MHz ARM® Cortex™-A8 RISC Processor
  • Up to 2000 ARM Cortex-A8 MIPS
• ARM Cortex-A8 Core
  • ARMv7 Architecture
    • In-Order, Dual-Issue, Superscalar Processor Core
    • NEON™ Multimedia Architecture
    • Supports Integer and Floating Point
    • Jazelle® RCT Execution Environment
• ARM Cortex-A8 Memory Architecture
  • 32KB of Instruction and Data Caches
  • 256KB of L2 Cache with ECC
  • 64KB of RAM, 48KB of Boot ROM
• 256KB of On-Chip Memory Controller (OCMC) RAM
• Imaging Subsystem (ISS)
  • Camera Sensor Connection
    • Parallel Connection for Raw (up to 16-Bit) and BT.656/BT.1120 (8- or 16-Bit)
    • CSI2 Serial Connection
  • Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
  • Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
  • Image Pipe (IPIPE) for Real-Time Image and Video Processing
  • Resizer
    • Resizing Image and Video From 1/16x to 8x
    • Generating Two Different Resizing Outputs Concurrently
    • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
• Face Detect (FD) Engine
  • Hardware Face Detection for up to 35 Faces Per Frame
• Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine
  • Encode, Decode, Transcode Operations
  • H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEG
• Media Controller
  • Controls the HDVPSS, HDVICP2, and ISS
• Endianness
  • ARM Instructions and Data – Little Endian
• HD Video Processing Subsystem (HDVPSS)
  • Two 165-MHz HD Video Capture Inputs
    • One 16- or 24-Bit Input, Splittable Into Dual 8-Bit SD Capture Ports
    • One 8-, 16-, or 24-Bit HD Input and 8-Bit SD Input Capture Port
  • Two 165-MHz HD Video Display Outputs
    • One 16-, 24-, or 30-Bit and One 16- or 24-Bit Output
  • Component HD Analog Output
  • Composite Analog Output
  • Digital HDMI 1.3 Transmitter with Integrated PHY
  • Advanced Video Processing Features Such as Scan, Format, and Rate Conversion
  • Three Graphics Layers and Compositors
• 32-Bit DDR2, DDR3, and DDR3L SDRAM Interface
  • Supports up to 400 MHz for DDR2, 533 MHz for DDR3, and 533 MHz for DDR3L
  • Up to Two x 16 Devices, 2GB of Total Address Space
  • Dynamic Memory Manager (DMM)
    • Programmable Multi-Zone Memory Mapping
    • Enables Efficient 2D Block Accesses
    • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
• General-Purpose Memory Controller (GPMC)
  • 8- or 16-Bit Multiplexed Address and Data Bus
  • 512MB of Total Address Space Divided Among up to 8 Chip Selects
  • Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
  • Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit or 512-Byte Hardware ECC for NAND
  • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and More
• Enhanced Direct Memory Access (EDMA) Controller
  • Four Transfer Controllers
  • 64 Independent DMA Channels
  • 8 QDMA Channels
• Dual USB 2.0 Ports with Integrated PHYs
  • USB2.0 High- and Full-Speed Clients
  • USB2.0 High-, Full-, and Low-Speed Hosts
  • Supports End Points 0-15
• Eight 32-Bit General-Purpose Timers (Timer1–8)
• One System Watchdog Timer (WDT0)
• Three Configurable UART/IrDA/CIR Modules
  • UART0 with Modem Control Signals
  • Supports up to 3.6864 Mbps
  • SIR, MIR, FIR (4.0 MBAUD), and CIR
• Four Serial Peripheral Interfaces (SPIs) (up to 48 MHz)
  • Each with Four Chip Selects
• Three MMC/SD/SDIO Serial Interfaces (up to 48 MHz)
  • Supporting up to 1-, 4-, or 8-Bit Modes
• Dual Controller Area Network (DCAN) Module
  • CAN Version 2 Part A, B
• Four Inter-Integrated Circuit (I²C Bus™) Ports
• Two Multichannel Audio Serial Ports (McASP)
  • Six Serializer Transmit and Receive Ports
  • Two Serializer Transmit and Receive Ports
  • DIT-Capable For S/PDIF (All Ports)
• Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHY
  • Direct Interface to 1 Hard Disk Drive
  • Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
  • Supports Port Multiplier and Command-Based Switching
• Real-Time Clock (RTC)
  • One-Time or Periodic Interrupt Generation
• Up to 125 General-Purpose I/O (GPIO) Pins
• One Spin Lock Module with up to 128 Hardware Semaphores
• One Mailbox Module with 12 Mailboxes
• On-Chip ARM ROM Bootloader (RBL)
• Power, Reset, and Clock Management
  • SmartReflex™ Technology (Level 2b)
  • Multiple Independent Core Power Domains
  • Multiple Independent Core Voltage Domains
  • Support for Multiple Operating Points per Voltage Domain
  • Clock Enable and Disable Control for Subsystems and Peripherals
• 32KB of Embedded Trace Buffer™ (ETB™) and 5-pin Trace Interface for Debug
• IEEE 1149.1 (JTAG) Compatible
• 609-Pin Pb-Free BGA Package (AAR Suffix), 0.8-mm Effective Pitch with Via Channel Technology to Reduce PCB Cost (0.5-mm Ball Spacing)
• 45-nm CMOS Technology
• 1.8- and 3.3-V Dual Voltage Buffers for General I/O

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