Gehäuseinformationen
| Gehäuse | Pins CFP (HSL) (HBD) | 64 |
| Betriebstemperaturbereich (°C) 25 to 25 |
| Gehäusemenge | Träger 14 | TUBE |
Merkmale von LMX2615-SP
- Radiation specifications:
- Single event latch-up >120 MeV-cm2/mg
- Total ionizing dose to 100 krad(Si)
- SMD 5962R1723601VXC
- 40-MHz to 15.2-GHz output frequency
- –110-dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
- 45 fs RMS jitter at 8 GHz (100 Hz to 100 MHz)
- Programmable output power
- PLL key
specifications:
- Figure of merit: –236 dBc/Hz
- Normalized 1/f noise: –129 dBc/Hz
- Up to 200-MHz phase detector frequency
- Synchronization of output phase across multiple devices
- Support for SYSREF with 9-ps resolution programmable delay
- 3.3-V single power supply operation
- 71 pre-selected pin modes
- 11 × 11 mm² 64-lead CQFP ceramic package
- Operating temperature range: –55°C to +125°C
- Supported by PLLatinum™ Simulator design tool
Beschreibung von LMX2615-SP
The LMX2615-SP is a high performance wideband phase-locked loop (PLL) with integrated voltage controlled oscillator (VCO) and voltage regulators that can output any frequency from 40 MHz and 15.2 GHz without a doubler, which eliminates the need for ½ harmonic filters. The VCO on this device covers an entire octave so the frequency coverage is complete down to 40 MHz. The high performance PLL with a figure of merit of –236 dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter.
The LMX2615-SP allows users to synchronize the output of multiple instances of the device. This means that deterministic phase can be obtained from a device in any use case including the one with fractional engine or output divider enabled. It also adds support for either generating or repeating SYSREF (compliant to JESD204B standard), making it an ideal low-noise clock source for high-speed data converters.
This device is fabricated in Texas Instruments’ advanced BiCMOS process and is available in a 64-lead CQFP ceramic package.