TMS320C54CST

• On-Chip ROM
  • 128K × 16-Bit Configured for Program Memory
  • Contains 14 TMS320™ DSP Algorithm Standard Compliant Telephony Algorithms
• 40K x 16-Bit On-Chip RAM Composed of Five Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
• CST Software in ROM:
  • Data Transfer (Modem up to V.32BIS 14400 bps)
  • Telephony Signals Processing (DTMF, CPTD, Caller ID)
  • Voice Processing (Echo Canceller, G726, VAD, CNG, AGC)
• Configurable in Either:
  • Chipset Mode: Stand-Alone Telephony/Data Modem (ROM-Only Code Execution)
  • Flex Mode: Code Execution From RAM, ROM, or External.
• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
• 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
• Data Bus With a Bus Holder Feature
• Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
• Enhanced External Parallel Interface (XIO2)
• Single-Instruction-Repeat and Block-Repeat Operations for Program Code
• Block-Memory-Move Instructions for Better Program and Data Management
• Instructions With a 32-Bit Long Word Operand
• Instructions With Two- or Three-Operand Reads
• Arithmetic Instructions With Parallel Store and Parallel Load
• Conditional Store Instructions
• Fast Return From Interrupt
• On-Chip Peripherals
  • Software-Programmable Wait-State Generator and Programmable Bank-Switching
  • On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
  • Two 16-Bit Timers
  • Six-Channel Direct Memory Access (DMA) Controller
  • Two Multichannel Buffered Serial Ports (McBSPs)
  • 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
  • Universal Asynchronous Receiver/ Transmitter (UART) With Integrated Baud Rate Generator
  • Integrated Direct Access Arrangement (DAA) Module
• Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
• CLKOUT Off Control to Disable CLKOUT
• On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
• 144-Pin Ball Grid Array (BGA) (GGU Suffix)
• 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
• 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
• 3.3-V I/O Supply Voltage
• 1.5-V Core Supply Voltage

All trademarks are the property of their respective owners.
TMS320 is a trademark of Texas Instruments.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307).
TMS320C54x is a trademark of Texas Instruments.