TMS320C6745

Name: TMS320C6745
Brand: TI
SKU: TMS320C6745
Price: 7.935 USD

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C674x Fließkomma-DSP mit geringem Stromverbrauch – 456MHz, QFP

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Datenblatt

document-pdfAcrobat TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor datasheet (Rev. F) (Englisch) PDF | HTML

Benutzerhandbücher

document-pdfAcrobat
TMS320C6745/C6747 DSP Technical Reference Manual (Rev. D) (Englisch)

Fehlerverzeichnis

document-pdfAcrobat
TMS320C6745 Fixed/Floating-Point DSP SE (Silicon Revs 3.0, 2.1, 2.0, 1.1, & 1.0) (Rev. G) (Englisch)

TMS320C6745

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Datenblatt

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Produktdetails

DSP type

1 C674x

DSP (max) (MHz)

375, 456

CPU

32-/64-bit

Operating system

TI-RTOS

Ethernet MAC

10/100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSP type

1 C674x

DSP (max) (MHz)

375, 456

CPU

32-/64-bit

Operating system

TI-RTOS

Ethernet MAC

10/100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

HLQFP (PTP)

176

676 mm² 26 x 26

Software Support
- TI DSP/BIOS™
- Chip Support Library and DSP Library
375- and 456-MHz TMS320C674x VLIW DSP
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 3648 MIPS and 2736 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 256KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
128KB of RAM Shared Memory (TMS320C6747 Only)
3.3-V LVCMOS I/Os (Except for USB Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)
- EMIFB
  - 32-Bit or 16-Bit SDRAM with 256-MB Address Space (TMS320C6747)
  - 16-Bit SDRAM with 128-MB Address Space (TMS320C6745)
Three Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- Autoflow Control Signals (CTS, RTS) on UART0 Only
- 16-Byte FIFO
- 16x or 13x Oversampling Option
LCD Controller (TMS320C6747 Only)
Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Realtime Unit (PRU) Cores
  - 32-Bit Load and Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled via Software to Save Power
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
USB 1.1 OHCI (Host) with Integrated PHY (USB1) (TMS320C6747 Only)
USB 2.0 OTG Port with Integrated PHY (USB0)
- USB 2.0 High- and Full-Speed Client (TMS320C6747)
- USB 2.0 Full-Speed Client (TMS320C6745)
- USB 2.0 High-, Full-, and Low-Speed Host (TMS320C6747)
- USB 2.0 Full- and Low-Speed Host (TMS320C6745)
- High-Speed Functionality Available on TMS320C6747 Device Only
- End Point 0 (Control)
- End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
Three Multichannel Audio Serial Ports (McASPs):
- TMS320C6747 Supports 3 McASPs
- TMS320C6745 Supports 2 McASPs
- Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable (McASP2)
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747 Only)
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
TMS320C6747 Device:
- 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
TMS320C6745 Device:
- 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
Commercial, Industrial, Extended, or Automotive Temperature

Software Support
- TI DSP/BIOS™
- Chip Support Library and DSP Library
375- and 456-MHz TMS320C674x VLIW DSP
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 3648 MIPS and 2736 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 256KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
128KB of RAM Shared Memory (TMS320C6747 Only)
3.3-V LVCMOS I/Os (Except for USB Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)
- EMIFB
  - 32-Bit or 16-Bit SDRAM with 256-MB Address Space (TMS320C6747)
  - 16-Bit SDRAM with 128-MB Address Space (TMS320C6745)
Three Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- Autoflow Control Signals (CTS, RTS) on UART0 Only
- 16-Byte FIFO
- 16x or 13x Oversampling Option
LCD Controller (TMS320C6747 Only)
Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Realtime Unit (PRU) Cores
  - 32-Bit Load and Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled via Software to Save Power
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
USB 1.1 OHCI (Host) with Integrated PHY (USB1) (TMS320C6747 Only)
USB 2.0 OTG Port with Integrated PHY (USB0)
- USB 2.0 High- and Full-Speed Client (TMS320C6747)
- USB 2.0 Full-Speed Client (TMS320C6745)
- USB 2.0 High-, Full-, and Low-Speed Host (TMS320C6747)
- USB 2.0 Full- and Low-Speed Host (TMS320C6745)
- High-Speed Functionality Available on TMS320C6747 Device Only
- End Point 0 (Control)
- End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
Three Multichannel Audio Serial Ports (McASPs):
- TMS320C6747 Supports 3 McASPs
- TMS320C6745 Supports 2 McASPs
- Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable (McASP2)
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747 Only)
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
TMS320C6747 Device:
- 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
TMS320C6745 Device:
- 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
Commercial, Industrial, Extended, or Automotive Temperature

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .

The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I²C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .

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	Typ	Titel		Datum
*	Data sheet	TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor datasheet (Rev. F)	PDF \| HTML	17 Jun 2014
*	Errata	TMS320C6745 Fixed/Floating-Point DSP SE (Silicon Revs 3.0, 2.1, 2.0, 1.1, & 1.0) (Rev. G)		17 Jun 2014
*	User guide	TMS320C6745/C6747 DSP Technical Reference Manual (Rev. D)		21 Sep 2016
	Application note	High-Speed Interface Layout Guidelines (Rev. J)	PDF \| HTML	24 Feb 2023
	Application note	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	19 Mai 2021
	User guide	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		01 Jun 2020
	Application note	Using DSPLIB FFT Implementation for Real Input and Without Data Scaling	PDF \| HTML	11 Jun 2019
	Application note	Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx		25 Apr 2019
	Application note	TMS320C6747/45/43 Power Consumption Summary		23 Apr 2019
	Application note	General Hardware Design/BGA PCB Design/BGA		22 Feb 2019
	Application note	OMAP-L13x / C674x / AM1x schematic review guidelines	PDF \| HTML	14 Feb 2019
	Application note	McASP Design Guide - Tips, Tricks, and Practical Examples		10 Jan 2019
	White paper	Designing professional audio mixers for every scenario		28 Jun 2018
	User guide	OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D)		21 Sep 2016
	User guide	System Analyzer User's Guide (Rev. F)		18 Nov 2013
	User guide	TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W)		21 Aug 2012
	User guide	TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U)		21 Aug 2012
	Application note	Using the OMAP-L1x7 Bootloader (Rev. G)		01 Jun 2012
	Application note	Using the TMS320C6747/45/43 Bootloader (Rev. C)		01 Jun 2012
	Application note	Introduction to TMS320C6000 DSP Optimization		06 Okt 2011
	User guide	TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F)		14 Sep 2011
	White paper	Software and Hardware Design Challenges Due to Dynamic Raw NAND Market		19 Mai 2011
	Application note	Power Solution Using Discrete DC/DC Converters and LDOs (Rev. B)		26 Aug 2010
	User guide	TMS320C674x DSP Megamodule Reference Guide (Rev. A)		03 Aug 2010
	User guide	TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B)		30 Jul 2010
	Application note	Power Solution using LDO's (Rev. A)		25 Mär 2010
	Application note	Power Solution using a Dual DCDC Converter and a LDO (Rev. A)		25 Mär 2010
	User guide	TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S)		18 Mär 2010
	User guide	TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q)		18 Mär 2010
	Application note	OMAP-L137 TMS320C6747/6745/6743 Pin Multiplexing Utility (Rev. A)		26 Sep 2009
	Application note	TMS320C6747/45/43 Complementary Products		23 Sep 2009
	White paper	Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core		24 Jun 2009
	Application note	TMS320C6747/45/43 & OMAP-L1x7 USB Downstream Host Compliance Testing		12 Mär 2009
	Application note	TMS320C6747/45/43 & OMAP-L1x7 USB Upstream Device Compliance Testing		12 Mär 2009
	Application note	TMS320C674x/OMAP-L1x USB Compliance Checklist		12 Mär 2009
	Application note	TMS320C6745 Technical Brief (Rev. B)		18 Feb 2009
	User guide	TMS320C674x DSP Cache User's Guide (Rev. A)		11 Feb 2009
	User guide	TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q)		15 Mai 2008
	User guide	TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O)		15 Mai 2008
	User guide	TMS320C6000 Assembly Language Tools v 6.0 Beta User's Guide (Rev. P)		31 Okt 2006
	User guide	TMS320C6000 Optimizing Compiler v 6.0 Beta User's Guide (Rev. N)		29 Jul 2005

Design und Entwicklung

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Debug-Tastkopf

TMDSEMU200-U — XDS200-USB-Debug-Tastkopf

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Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7). Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

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Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-C6747 — Prozessor-SDK für C6747-Prozessoren mit TI-RTOS-Support

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TMS320C6727 — C67x Fließkomma-DSP – bis zu 250MHz, McASP, 32-Bit-EMIFA

TMS320C6727B — C67x Fließkomma-DSP – bis zu 350 MHz, McASP, 32-Bit-EMIFA

TMS320C6743 — Energieeffizienter C674x-Fließkomma-DSP – 375 MHz

TMS320C6745 — C674x Fließkomma-DSP mit geringem Stromverbrauch – 456MHz, QFP

TMS320C6747 — C674x Fließkomma-DSP mit geringem Stromverbrauch – 456 MHz, PBGA

TMS320DM642Q — Digitaler Festkomma-Signalprozessor für Video/Bildverarbeitung

TMS320DM6431Q — Digitaler Medienprozessor, bis zu 2400 MIPS, 300-MHz-Taktrate

TMS320DM6435Q — Digitaler Medienprozessor, bis zu 4800 MIPS, 600 MHz-Taktrate, 1 McASP, 1 McBSP

TMS320DM6437Q — Digitaler Medienprozessor, bis zu 4800 MIPS, 600-MHz-Taktrate, 1 McASP, 2 McBSP

TMS320DM6441 — DaVinci Digital-Media-System-on-Chip

TMS320DM6467T — System-on-Chip für digitale Medien

TMS320DM647 — Digital-Media-Prozessor

Download-Optionen

Treiber oder Bibliothek

C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

Unterstützte Produkte und Hardware

Produkte

ARM-basierte Prozessoren

OMAPL137-HT — C674x Fließkomma-DSP mit geringem Stromverbrauch und Arm-Prozessor für hohe Temperaturen – bis zu 45

OMAPL138B-EP — Optimiertes Produkt energieeffizienter C674x-Fließkomma-DSP + ARM9-Prozessor – 345 MHz

TMS320DM8127 — DaVinci Digital-Media-Prozessor

Digitale Signalprozessoren (DSPs)

SM320C6424-EP — Verbessertes Produkt, C6424 Festkomma-DSP

SM320C6472-HIREL — Hochzuverlässiger 6 Core C6472 Festkomma-DSP

SM320C6678-HIREL — Hochzuverlässiges Produkt mit hoher Leistung, 8-Kern-C6678 Fest- und Gleitkomma-DSP

SM320C6701 — Single-Core-C67x-Fließkomma-DSP für militärische Anwendungen – bis zu 167 MHz

SM320C6701-EP — Verbessertes Produkt – C6701 Fließkomma-DSP

SMJ320C6203 — C62x Festkomma-DSP in militärischer Qualität – Keramikgehäuse

SMJ320C6701 — C67x-Fließkomma-DSP in Militärqualität – Keramikgehäuse

SMJ320C6701-SP — Weltraumtauglicher C6701-Fließkomma-DSP – strahlungstolerant, Klasse V mit Keramikgehäuse

SMV320C6727B-SP — Raumfahrttauglicher C6727B Gleitkomma-DSP – strahlungstolerant, Klasse V mit Keramikgehäuse

TMS320C6202B — C62x Festkomma-DSP – bis zu 300 MHz, 384 KB

TMS320C6203B — C62x Festkomma-DSP – bis zu 300 MHz, 896 KB

TMS320C6211B — C62x Festkomma-DSP – bis zu 167MHz

TMS320C6421Q — C64x+ Festkomma-DSP – bis zu 600 MHz, 8 Bit EMIFA, 16-Bit DDR2

TMS320C6424Q — C64x+ Festkomma-DSP – bis zu 600 MHz, 16/8-Bit EMIFA, 32/16 Bit DDR2

TMS320C6452 — C64x+ Festkomma-DSP – bis zu 900 MHz, 1 Gbps-Ethernet

TMS320C6454 — C64x+ Festkomma-DSP – bis zu 1GHz, 64-Bit EMIFA, 32/16 Bit DDR2, 1 Gbps-Ethernet

TMS320C6455 — C64x+ Festkomma-DSP – bis zu 1,2 GHz, 64-Bit EMIFA, 32/16 Bit DDR2, Ethernet 1Gbit/s