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TS3DDR4000

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12-Kanal-DDR2-, DDR3- und DDR4-Schalter, 3,3 V, 2:1 (SPDT)

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Datenblatt

TS3DDR4000

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Produktdetails

Protocols DDR2, DDR3, DDR4, MIPI Configuration 2:1 SPDT Number of channels 12 Supply voltage (max) (V) 3.6 Supply voltage (min) (V) 2.375 Ron (typ) (mΩ) 8300 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.3 Supply current (typ) (µA) 40 ESD HBM (typ) (kV) 3 Operating temperature range (°C) -40 to 85 Crosstalk (dB) -68 COFF (typ) (pF) 1 CON (typ) (pF) 0.5 Off isolation (typ) (dB) -34 OFF-state leakage current (max) (µA) 5 Ron (max) (mΩ) 11200 Ron channel match (max) (Ω) 1 RON flatness (typ) (Ω) 0.6 Turnoff time (disable) (max) (ns) 65 Turnon time (enable) (max) (ns) 65 VIH (min) (V) 1.4 VIL (max) (V) 0.5
Protocols DDR2, DDR3, DDR4, MIPI Configuration 2:1 SPDT Number of channels 12 Supply voltage (max) (V) 3.6 Supply voltage (min) (V) 2.375 Ron (typ) (mΩ) 8300 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.3 Supply current (typ) (µA) 40 ESD HBM (typ) (kV) 3 Operating temperature range (°C) -40 to 85 Crosstalk (dB) -68 COFF (typ) (pF) 1 CON (typ) (pF) 0.5 Off isolation (typ) (dB) -34 OFF-state leakage current (max) (µA) 5 Ron (max) (mΩ) 11200 Ron channel match (max) (Ω) 1 RON flatness (typ) (Ω) 0.6 Turnoff time (disable) (max) (ns) 65 Turnon time (enable) (max) (ns) 65 VIH (min) (V) 1.4 VIL (max) (V) 0.5
NFBGA (ZBA) 48 24 mm² 8 x 3
  • Wide VDD Range: 2.375 V – 3.6 V
  • High Bandwidth: 5.6 GHz Typical (single-ended); 6.0 GHz Typical (differential)
  • Low Switch On-Resistance (RON): 8 Ω Typical
  • Low Bit-to-Bit Skew: 3ps Typical; 6ps Max across All Channels
  • Low Crosstalk: –34 dB Typical at 1067 MHz
  • Low Operating Current: 40 µA Typical
  • Low-Power Mode with Low Current Consumption: 2 µA Typical
  • IOFF Protection Prevents Current Leakage in Powered Down State (VDD = 0 V)
  • Supports POD_12, SSTL_12, SSTL_15 and SSTL_18 Signaling
  • ESD Performance:
    • 3-kV Human Body Model (A114B, Class II)
    • 1-kV Charged Device Model (C101)
  • 8 mm x 3 mm 48-balls 0.65-mm Pitch ZBA Package
  • Wide VDD Range: 2.375 V – 3.6 V
  • High Bandwidth: 5.6 GHz Typical (single-ended); 6.0 GHz Typical (differential)
  • Low Switch On-Resistance (RON): 8 Ω Typical
  • Low Bit-to-Bit Skew: 3ps Typical; 6ps Max across All Channels
  • Low Crosstalk: –34 dB Typical at 1067 MHz
  • Low Operating Current: 40 µA Typical
  • Low-Power Mode with Low Current Consumption: 2 µA Typical
  • IOFF Protection Prevents Current Leakage in Powered Down State (VDD = 0 V)
  • Supports POD_12, SSTL_12, SSTL_15 and SSTL_18 Signaling
  • ESD Performance:
    • 3-kV Human Body Model (A114B, Class II)
    • 1-kV Charged Device Model (C101)
  • 8 mm x 3 mm 48-balls 0.65-mm Pitch ZBA Package

The TS3DDR4000 is 1:2 or 2:1 high speed DDR2/DDR3/DDR4 switch that offers 12-bit wide bus switching. The A port can be switched to the B or C port for all bits simultaneously. Designed for operation in DDR2, DDR3 and DDR4 memory bus systems, the TS3DDR4000 uses a proprietary architecture that delivers high bandwidth (single-ended –3dB bandwidth at 5.6 GHz), low insertion loss at low frequency, and very low propagation delay. The TS3DDR4000 is 1.8 V logic compatible, and all switches are bi-directional for added design flexibility. The TS3DDR4000 also offers a low-power mode, in which all channels become high-Z and the device consumes minimal power.

The TS3DDR4000 is 1:2 or 2:1 high speed DDR2/DDR3/DDR4 switch that offers 12-bit wide bus switching. The A port can be switched to the B or C port for all bits simultaneously. Designed for operation in DDR2, DDR3 and DDR4 memory bus systems, the TS3DDR4000 uses a proprietary architecture that delivers high bandwidth (single-ended –3dB bandwidth at 5.6 GHz), low insertion loss at low frequency, and very low propagation delay. The TS3DDR4000 is 1.8 V logic compatible, and all switches are bi-directional for added design flexibility. The TS3DDR4000 also offers a low-power mode, in which all channels become high-Z and the device consumes minimal power.
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Technische Dokumentation

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Typ Titel Datum
* Data sheet TS3DDR4000 12-bits 1:2 high speed DDR2/DDR3/DDR4 switch/multiplexer datasheet (Rev. C) PDF | HTML 18 Mär 2019
Product overview Mipi Switches PDF | HTML 14 Jan 2022
Technical article Memory switches bring reliability and speed to clouding computing PDF | HTML 05 Jan 2016
EVM User's guide TS3DDR4000 EVM User Guide 20 Feb 2015
Application note Preventing Excess Power Consumption on Analog Switches 03 Jul 2008
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004

Design und Entwicklung

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Evaluierungsplatine

TS3DDR4000-EVM — TS3DDR4000-Evaluierungsmodul

The TS3DDR4000-EVM is an evaluation module for TI’s 12-bit high-speed DDR2, DDR3 and DDR4 switch/multiplexer.  The module lets you easily evaluate functional switching and logic implementation.

Benutzerhandbuch: PDF
Nicht verfügbar auf TI.com
Simulationsmodell

TS3DDR4000 HSpice Model

SCDM168.ZIP (5037 KB) - HSpice Model
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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
NFBGA (ZBA) 48 Ultra Librarian
Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

Bestellen & Qualität

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