Produktdetails

Configuration 2:1 SPDT Number of channels 1 Power supply voltage - single (V) 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 0.5 CON (typ) (pF) 133 ON-state leakage current (max) (µA) 0.2 Supply current (typ) (µA) 0.01 Bandwidth (MHz) 43 Operating temperature range (°C) -40 to 85 Features 1.8-V compatible control inputs, Break-before-make Input/output continuous current (max) (mA) 450 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
Configuration 2:1 SPDT Number of channels 1 Power supply voltage - single (V) 2.5, 3.3, 5 Protocols Analog Ron (typ) (Ω) 0.5 CON (typ) (pF) 133 ON-state leakage current (max) (µA) 0.2 Supply current (typ) (µA) 0.01 Bandwidth (MHz) 43 Operating temperature range (°C) -40 to 85 Features 1.8-V compatible control inputs, Break-before-make Input/output continuous current (max) (mA) 450 Rating Catalog Drain supply voltage (max) (V) 5.5 Supply voltage (max) (V) 5.5
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25
  • Specified Break-Before-Make Switching
  • Low ON-State Resistance (0.75 Max)
  • Control Inputs Referenced to VIO
  • Low Charge Injection
  • Excellent ON-State Resistance Matching
  • Low Total Harmonic Distortion (THD)
  • 2.25-V to 5.5-V Power Supply (V+)
  • 1.65-V to 1.95-V Logic Supply (VIO)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 4000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
    • 400-V Machine Model (A115-A)
  • COM Port to GND
    • 8000-V Human-Body Model
      (A114-B, Class II)
    • ±15-kV Contact Discharge (IEC 61000-4-2)
  • APPLICATIONS
    • Cell Phones
    • PDAs
    • Portable Instrumentation

  • Specified Break-Before-Make Switching
  • Low ON-State Resistance (0.75 Max)
  • Control Inputs Referenced to VIO
  • Low Charge Injection
  • Excellent ON-State Resistance Matching
  • Low Total Harmonic Distortion (THD)
  • 2.25-V to 5.5-V Power Supply (V+)
  • 1.65-V to 1.95-V Logic Supply (VIO)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 4000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
    • 400-V Machine Model (A115-A)
  • COM Port to GND
    • 8000-V Human-Body Model
      (A114-B, Class II)
    • ±15-kV Contact Discharge (IEC 61000-4-2)
  • APPLICATIONS
    • Cell Phones
    • PDAs
    • Portable Instrumentation

The TS5A6542 is a single-pole double-throw (SPDT) analog switch that is designed to operate from 2.25 V to 5.5 V. The device offers a low ON-state resistance with an excellent channel-to-channel ON-state resistance matching, and the break-before-make feature to prevent signal distorion during the transferring of a signal from one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very low power. These features make this device suitable for portable audio applications.

The TS5A6542 has a separate logic supply pin (VIO) that is characterized to operate from 1.65 V to 1.95 V. VIO powers the control circuitry, which allows the TS5A6542 to be controlled by 1.8-V signals.

The TS5A6542 is a single-pole double-throw (SPDT) analog switch that is designed to operate from 2.25 V to 5.5 V. The device offers a low ON-state resistance with an excellent channel-to-channel ON-state resistance matching, and the break-before-make feature to prevent signal distorion during the transferring of a signal from one path to another. The device has excellent total harmonic distortion (THD) performance and consumes very low power. These features make this device suitable for portable audio applications.

The TS5A6542 has a separate logic supply pin (VIO) that is characterized to operate from 1.65 V to 1.95 V. VIO powers the control circuitry, which allows the TS5A6542 to be controlled by 1.8-V signals.

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Typ Titel Datum
* Data sheet TS5A6542 0.75-Ohm SPDT Analog Switch With Input Logic Translation datasheet (Rev. C) 11 Dez 2009
Application note High-Efficiency Charging for TWS Using a 2-Pin Interface Application Report (Rev. A) PDF | HTML 16 Mai 2023
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 Jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 Dez 2021
Application note Preventing Excess Power Consumption on Analog Switches 03 Jul 2008
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004

Design und Entwicklung

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Schnittstellenadapter

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The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
Benutzerhandbuch: PDF
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HSPICE MODEL OF TS5A6542

SCEJ226.ZIP (90 KB) - HSpice Model
Simulationsmodell

TS5A6542 IBIS Model

SCEM514.ZIP (67 KB) - IBIS Model
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
DSBGA (YZP) 8 Ultra Librarian

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