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UCC27524

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5-A/5-A-Zweikanal-Gate-Treiber mit 5-V-UVLO, Aktivierung und 1-ns-Delay Matching

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UCC27524

AKTIV
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Produktdetails

Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) 0 Rating Catalog Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
Number of channels 2 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Enable pin Operating temperature range (°C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) 0 Rating Catalog Undervoltage lockout (typ) (V) 4 Driver configuration Dual, Non-Inverting
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9 PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6 WSON (DSD) 8 9 mm² 3 x 3
  • Industry-standard pin out
  • Two independent gate-drive channels
  • 5A peak source and sink-drive current
  • Independent-enable function for each output
  • TTL and CMOS compatible logic threshold independent of supply voltage
  • Hysteretic-logic thresholds for high noise immunity
  • Ability to handle negative voltages (–5V) at inputs
  • Inputs and enable pin-voltage levels not restricted by VDD pin bias supply voltage
  • 4.5V to 18V single-supply range
  • Outputs held low during VDD-UVLO (ensures glitch-free operation at power up and power down)
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (6ns and 10ns typical)
  • 1ns typical delay matching between two channels
  • Two outputs are paralleled for higher drive current
  • Outputs held in low when inputs floating
  • SOIC-8, HVSSOP-8 PowerPAD™ package options
  • Operating junction temperature range of –40 to 150°C
  • Industry-standard pin out
  • Two independent gate-drive channels
  • 5A peak source and sink-drive current
  • Independent-enable function for each output
  • TTL and CMOS compatible logic threshold independent of supply voltage
  • Hysteretic-logic thresholds for high noise immunity
  • Ability to handle negative voltages (–5V) at inputs
  • Inputs and enable pin-voltage levels not restricted by VDD pin bias supply voltage
  • 4.5V to 18V single-supply range
  • Outputs held low during VDD-UVLO (ensures glitch-free operation at power up and power down)
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (6ns and 10ns typical)
  • 1ns typical delay matching between two channels
  • Two outputs are paralleled for higher drive current
  • Outputs held in low when inputs floating
  • SOIC-8, HVSSOP-8 PowerPAD™ package options
  • Operating junction temperature range of –40 to 150°C

The UCC27524 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524 adds the ability to handle –5V directly at the input pins for increased robustness. The UCC27524 is a dual non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524 is capable of delivering high-peak current pulses of up to 5A source and 5A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay typically 17ns. In addition, the drivers feature matched internal propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For safety purpose, internal pull-up and pull-down resistors on the input pins of the UCC27524 ensure that outputs are held LOW when input pins are in floating condition. UCC27524 features Enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

UCC27524 family of devices are available in SOIC-8 (D), VSSOP-8 with exposed pad (DGN) packages and 3mm × 3mm WSON-8 with exposed pad (DSD) packages package.

The UCC27524 device is a dual-channel, high-speed, low-side, gate-driver device capable of effectively driving MOSFET and IGBT power switches. The UCC27524 adds the ability to handle –5V directly at the input pins for increased robustness. The UCC27524 is a dual non-inverting driver. Using a design that inherently minimizes shoot-through current, the UCC27524 is capable of delivering high-peak current pulses of up to 5A source and 5A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay typically 17ns. In addition, the drivers feature matched internal propagation delays between the two channels which are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with a single input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

For safety purpose, internal pull-up and pull-down resistors on the input pins of the UCC27524 ensure that outputs are held LOW when input pins are in floating condition. UCC27524 features Enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

UCC27524 family of devices are available in SOIC-8 (D), VSSOP-8 with exposed pad (DGN) packages and 3mm × 3mm WSON-8 with exposed pad (DSD) packages package.
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Technische Dokumentation

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Typ Titel Datum
* Data sheet UCC27524 Dual 5A, High-Speed, Low-Side Gate Driver With Negative Input Voltage Capability datasheet PDF | HTML 13 Jun 2024
Application note Selecting Gate Drivers for HVAC Systems PDF | HTML 04 Apr 2024
Application note Why use a Gate Drive Transformer? PDF | HTML 04 Mär 2024
Application note Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs PDF | HTML 22 Jan 2024
Application note Static Magnet Power Supply Design for Magnetic Resonance Imaging Application PDF | HTML 22 Jan 2024
Application note Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver PDF | HTML 10 Nov 2021
More literature Troubleshooting gate drive circuits in automotive and industrial applications 23 Mär 2021
Application brief External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Application note Improving Efficiency of DC-DC Conversion through Layout 07 Mai 2019
Application brief How to overcome negative voltage transients on low-side gate drivers' inputs 18 Jan 2019
Application brief High-Side Cutoff Switches for High-Power Automotive Applications (Rev. A) 26 Nov 2018
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 29 Okt 2018
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
Application brief Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole 16 Mär 2018
More literature Design review of a 2-kW parallelable power supply module 17 Aug 2016
More literature Design review of a 2-kW parallelable power supply module (PPT) 17 Aug 2016
More literature Design Review of a Full-Featured 350-W Offline Power Converter 29 Okt 2013

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