Inicio Convertidores de datos Convertidores analógico-digitales (ADC) ADC de alta velocidad (≥ 10 MSPS)
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Convertidores de datos
Convertidores analógico-digitales (ADC)
ADC de alta velocidad (≥ 10 MSPS)

ADC12D1600RF

ACTIVO

Convertidor analógico a digital (ADC) de muestreo de RF de 12 bits, 1,6 GSPS dobles o 3,2 GSPS simpl

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ADC12D1600RF

ACTIVO
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Detalles del producto

Sample rate (max) (Msps) 1600, 3200 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 59 ENOB (Bits) 9.4 SFDR (dB) 75 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1600, 3200 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3880 Architecture Folding Interpolating SNR (dB) 59 ENOB (Bits) 9.4 SFDR (dB) 75 Operating temperature range (°C) -40 to 85 Input buffer Yes
PBGA (NXA) 292 729 mm² 27 x 27
  • Excellent Noise and Linearity up to and Above fIN =
    2.7 GHz
  • Configurable to Either 3.2 or 2 GSPS Interleaved
    or 1600 or 1000 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High
    Sampling Rate Apps
  • Pin-Compatible With ADC10D1x00, ADC12D1x00
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog
    Inputs
  • Interleaved Timing Automatic and Manual Skew
    Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust
    Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution 12 Bits
    • Interleaved 3.2- and 2-GSPS ADC
      • IMD3 (Fin = 2.7 GHz at –13 dBFS) –63.7/–73
        dBFS (Typical)
      • IMD3 (Fin = 2.7 GHz at –16 dBFS) –66.7/–85
        dBFS (Typical)
      • Noise Floor –154.6/–154 dBm/Hz (Typical)
      • Power 3.94/3.42 W (Typical)
    • Dual 1600/1000 MSPS ADC, Fin = 498 MHz
      • ENOB 9.2/9.4 Bits (Typical)
      • SNR 58.2/58.8 dB (Typical)
      • SFDR 66.7/71.9 dBc (Typical)
      • Power per Channel 1.97/1.71 W (Typical)
  • Excellent Noise and Linearity up to and Above fIN =
    2.7 GHz
  • Configurable to Either 3.2 or 2 GSPS Interleaved
    or 1600 or 1000 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High
    Sampling Rate Apps
  • Pin-Compatible With ADC10D1x00, ADC12D1x00
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog
    Inputs
  • Interleaved Timing Automatic and Manual Skew
    Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust
    Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution 12 Bits
    • Interleaved 3.2- and 2-GSPS ADC
      • IMD3 (Fin = 2.7 GHz at –13 dBFS) –63.7/–73
        dBFS (Typical)
      • IMD3 (Fin = 2.7 GHz at –16 dBFS) –66.7/–85
        dBFS (Typical)
      • Noise Floor –154.6/–154 dBm/Hz (Typical)
      • Power 3.94/3.42 W (Typical)
    • Dual 1600/1000 MSPS ADC, Fin = 498 MHz
      • ENOB 9.2/9.4 Bits (Typical)
      • SNR 58.2/58.8 dB (Typical)
      • SFDR 66.7/71.9 dBc (Typical)
      • Power per Channel 1.97/1.71 W (Typical)

The 12-bit 3.2- and 2-GSPS ADC12D1x00RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D1x00RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 3rd Nyquist zone

The ADC12D1x00RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common-mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to 85°C.

The 12-bit 3.2- and 2-GSPS ADC12D1x00RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D1x00RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 3rd Nyquist zone

The ADC12D1x00RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common-mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to 85°C.
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Documentación técnica

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Tipo Título Fecha
* Data sheet ADC12D1x00RF 12-Bit, 3.2-GSPS and 2-GSPS RF-Sampling ADC datasheet (Rev. H) PDF | HTML 31 ago 2015
Application note AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 03 feb 2017
Application note Wide Bandwidth Receiver Implementation by Interleaving Two Giga-Sampling ADCs 07 dic 2015
Application note Signal Chain Noise Figure Analysis 29 oct 2014
Application note Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs 06 ago 2014
Application note Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat 09 dic 2013
Application note AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 01 may 2013
User guide Schematic and Layout Recommendations for the GSPS ADC 29 abr 2013
Application note AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 26 abr 2013
Application note From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 18 dic 2012
Product overview ADC12Dxx00RF Direct RF-Sampling ADC Family 16 may 2012
User guide 12-Bit, Dual 1.6/1.8 GSPS or Single 3.2/3.6 GSPS A/D Converter Ref Bd User Guide 25 ene 2012

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

ADC-LD-BB — Placa balun ADC de baja distorsión

One ADC-LD-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

Guía del usuario: PDF
No disponible en TI.com
Soporte de software

WAVEVISION5 — WaveVision 5 Software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

Productos y hardware compatibles

Productos y hardware compatibles

Productos
ADC de alta velocidad (≥ 10 MSPS)
ADC08D1020 — Convertidor analógico a digital (ADC) de 8 bits, 1,0 GSPS dobles o 2,0 GSPS simples ADC08D1520 — Convertidor analógico a digital (ADC) de 8 bits, 1,5 GSPS dobles o 3,0 GSPS simples ADC10D1000 — Convertidor analógico a digital (ADC) de 10 bits, 1,0 GSPS dobles o 2,0 GSPS simples ADC10D1500 — Convertidor analógico a digital (ADC) de 10 bits, 1,5 GSPS dobles o 3,0 GSPS simples ADC10DV200 — Convertidor analógico a digital (ADC) de dos canales, 10 bits y 200 MSPS ADC12D1000 — Convertidor analógico a digital (ADC) de 12 bits, 1,0 GSPS dobles o 2,0 GSPS simples ADC12D1000RF — Convertidor analógico a digital (ADC) de muestreo de RF de 12 bits, 1,0 GSPS dobles o 2,0 GSPS simpl ADC12D1600 — Convertidor analógico a digital (ADC) de 12 bits, 1,6 GSPS dobles o 3,2 GSPS simples ADC12D1600RF — Convertidor analógico a digital (ADC) de muestreo de RF de 12 bits, 1,6 GSPS dobles o 3,2 GSPS simpl ADC12D1800 — Convertidor analógico a digital (ADC) de 12 bits, 1,8 GSPS dobles o 3,6 GSPS simples ADC12D1800RF — Convertidor analógico a digital (ADC) de muestreo de RF de 12 bits, 1,8 GSPS dobles o 3,6 GSPS simpl ADC12D500RF — Convertidor analógico a digital (ADC) de muestreo de RF de 12 bits, 500 MSPS dobles o 1,0 GSPS simpl ADC12D800RF — Convertidor analógico a digital (ADC) de muestreo de RF de 12 bits, 800 MSPS dobles o 1,6 GSPS simpl ADC14DC080 — Convertidor analógico a digital (ADC) de dos canales, 14 bits, 80 MSPS y ancho de banda de entrada d ADC16DV160 — Convertidor analógico a digital (ADC) de dos canales, 16 bits y 160 MSPS ADC16V130 — Convertidor analógico a digital (ADC) de 16 bits y 130 MSPS
Desarrollo de hardware
Placa de evaluación
ADC12D1600RB — Placa de referencia ADC de 12 bits, 1,6-/1,8 GSPS dobles o 3,2-/3,6 GSPS simples ADC16DV160HFEB — Placa de evaluación ADC16DV160HFEB LM98640CVAL — Interfaz analógica de doble canal, 14 bits y 40 MSPS con salida LVDS WAVEVSN-BRD-5.1 — Placa de captura de datos WaveVision 5 (versión 5.1)
Software
Software de aplicación y estructura
WAVEVISION5 — Software de adquisición y análisis de datos
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Modelo de simulación

ADC12D1000 IBIS Model

SNAM014.ZIP (41 KB) - IBIS Model
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Diseños de referencia

TIDA-00113 — ADC de impulsión de GSPS en el modo de canal único o de canal doble para aplicaciones de ancho de ba

This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications.  The tradeoffs considered include balun construction, insertion loss, dynamic (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00479 — Diseño de referencia de fuentes de reloj óptimas para ADC de GSPS

The ADC12D1600RFRB reference design provides a platform to demonstrate a high speed digitizer application which incorporates clocking, power management, and signal processing. The reference design utilizes the 1.6 GSPS ADC12D1600RF device, onboard FPGA Xilinx Virtex 4, and high performance clock (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00071 — Recomendaciones de esquemas y diseños para el ADC de muestra por segundo (GSPS) de Giga

This reference design is a guide to the schematics and layout for the system designer using a GSPS ADC in their system. Use this reference design along with the datasheet — the datasheet is always the final authority. Also, the ADC1xDxxxx(RF)RB Reference Board provides a useful reference (...)
Guía del usuario: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
PBGA (NXA) 292 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

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  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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