Operates from ±5V to ±18V Supplies
Less Than 10 μs Acquisition Time
TTL, PMOS, CMOS Compatible Logic Input
0.5 mV Typical Hold Step at C_h = 0.01 μF
Low Input Offset
0.002% Gain Accuracy
Low Output Noise in Hold Mode
Input Characteristics Do Not Change During Hold Mode
High Supply Rejection Ratio in Sample or Hold
Wide Bandwidth
Space Qualified
Logic Inputs on the LF198 are Fully Differential with Low Input Current, Allowing Direct Connection to TTL, PMOS, and CMOS. Differential Threshold is 1.4V. The LF198 will Operate from ±5V to ±18V Supplies.

All trademarks are the property of their respective owners.

Operates from ±5V to ±18V Supplies
Less Than 10 μs Acquisition Time
TTL, PMOS, CMOS Compatible Logic Input
0.5 mV Typical Hold Step at C_h = 0.01 μF
Low Input Offset
0.002% Gain Accuracy
Low Output Noise in Hold Mode
Input Characteristics Do Not Change During Hold Mode
High Supply Rejection Ratio in Sample or Hold
Wide Bandwidth
Space Qualified
Logic Inputs on the LF198 are Fully Differential with Low Input Current, Allowing Direct Connection to TTL, PMOS, and CMOS. Differential Threshold is 1.4V. The LF198 will Operate from ±5V to ±18V Supplies.

All trademarks are the property of their respective owners.

The LF198 is a monolithic sample-and-hold circuit which utilizes BI-FET technology to obtain ultra-high dc accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, dc gain accuracy is 0.002% typical and acquisition time is as low as 6 μs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset drift. The wide bandwidth allows the LF198 to be included inside the feedback loop of 1 MHz op amps without having stability problems. Input impedance of 10¹⁰Ω allows high source impedances to be used without degrading accuracy.

P-channel junction FET's are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min with a 1 μF hold capacitor. The JFET's have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design ensures no feed-through from input to output in the hold mode, even for input signals equal to the supply voltages.

The LF198 is a monolithic sample-and-hold circuit which utilizes BI-FET technology to obtain ultra-high dc accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, dc gain accuracy is 0.002% typical and acquisition time is as low as 6 μs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset drift. The wide bandwidth allows the LF198 to be included inside the feedback loop of 1 MHz op amps without having stability problems. Input impedance of 10¹⁰Ω allows high source impedances to be used without degrading accuracy.

P-channel junction FET's are combined with bipolar devices in the output amplifier to give droop rates as low as 5 mV/min with a 1 μF hold capacitor. The JFET's have much lower noise than MOS devices used in previous designs and do not exhibit high temperature instabilities. The overall design ensures no feed-through from input to output in the hold mode, even for input signals equal to the supply voltages.

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	Tipo	Título		Fecha
*	Data sheet	LF198JAN Monolithic Sample-and-Hold Circuits datasheet (Rev. A)		20 mar 2013
	Application brief	DLA Approved Optimizations for QML Products (Rev. B)	PDF \| HTML	17 may 2024
	Selection guide	TI Space Products (Rev. J)		12 feb 2024
	More literature	TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A)		31 ago 2023
	Application note	Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A)	PDF \| HTML	17 nov 2022
	Application note	Single-Event Effects Confidence Interval Calculations (Rev. A)	PDF \| HTML	19 oct 2022

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LF198JAN-SP

Circuito de muestra y retención monolítico

LF198JAN-SP

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