Inicio Microcontroladores (MCU) y procesadores Procesadores basados en Arm
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Microcontroladores (MCU) y procesadores
Procesadores basados en Arm

TDA4AL-Q1

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Sistema en un chip de automoción para la cámara frontal y el control del dominio ADAS mediante senso

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TDA4AL-Q1

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Detalles del producto

Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors 2 Arm Cortex-R5F, MCU Island of 2 Arm Cortex-R5F (lockstep opt) CPU 64-bit Display type 1 DSI, MIPI DPI Ethernet MAC 2-Port 10/100/1000 Hardware accelerators 1 deep learning accelerator, 1 depth and motion accelerator, 1 video encode accelerator, 1 vision pre-processing accelerator Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125
Arm CPU 2 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors 2 Arm Cortex-R5F, MCU Island of 2 Arm Cortex-R5F (lockstep opt) CPU 64-bit Display type 1 DSI, MIPI DPI Ethernet MAC 2-Port 10/100/1000 Hardware accelerators 1 deep learning accelerator, 1 depth and motion accelerator, 1 video encode accelerator, 1 vision pre-processing accelerator Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125
FCBGA (ALZ) 770 529 mm² 23 x 23

Processor cores:

  • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Up to Six Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Four (TDA4VE) or Two (TDA4AL/TDA4VL)Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s (TDA4VE and TDA4VL)
  • Custom-designed interconnect fabric supporting near max processing entitlement

Memory subsystem:

  • Up to 4MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Two (TDA4VE) or One (TDA4AL/TDA4VL) 32-bit data bus with inline ECC up to 17 GB/s per EMIF
  • General-Purpose Memory Controller (GPMC)
  • One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB on-chip SRAM in MAIN domain, protected by ECC

Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
  • Developed for functional safety applications
  • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
  • Systematic capability up to ASIL-D/SIL-3 targeted
  • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
  • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
  • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
    • ISO 26262 planned

Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

  • One PCI-Express (PCIe) Gen3 controllers
    • Up to four lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Two CSI2.0 4L RX plus Two CSI2.04L TX

Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

Display subsystem:

  • One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L TX (up to 2.5K)
  • One eDP 4L (TDA4VE/TDA4VL)
  • One DPI

Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

Video acceleration:

  • TDA4VE: H.264/H.265 Encode/Decode (up to 480 MP/s)
  • TDA4AL: H.264/H.265 Encode only (up to 480 MP/s)
  • TDA4VL: H.264/H.265 Encode/Decode (up to 240 MP/s)

Ethernet:

  • Two RMII/RGMII interfaces

Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI, and
    • One QSPI

System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL-D / SIL-3 targeted
  • Flexible mapping to support different use cases

Processor cores:

  • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2 GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Up to Six Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Four (TDA4VE) or Two (TDA4AL/TDA4VL)Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s (TDA4VE and TDA4VL)
  • Custom-designed interconnect fabric supporting near max processing entitlement

Memory subsystem:

  • Up to 4MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Two External Memory Interface (EMIF) modules with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Two (TDA4VE) or One (TDA4AL/TDA4VL) 32-bit data bus with inline ECC up to 17 GB/s per EMIF
  • General-Purpose Memory Controller (GPMC)
  • One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB on-chip SRAM in MAIN domain, protected by ECC

Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
  • Developed for functional safety applications
  • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
  • Systematic capability up to ASIL-D/SIL-3 targeted
  • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
  • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
  • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
  • Safety-related certification
    • ISO 26262 planned

Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

High speed serial interfaces:

  • One PCI-Express (PCIe) Gen3 controllers
    • Up to four lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Two CSI2.0 4L RX plus Two CSI2.04L TX

Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

Display subsystem:

  • One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L TX (up to 2.5K)
  • One eDP 4L (TDA4VE/TDA4VL)
  • One DPI

Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

Video acceleration:

  • TDA4VE: H.264/H.265 Encode/Decode (up to 480 MP/s)
  • TDA4AL: H.264/H.265 Encode only (up to 480 MP/s)
  • TDA4VL: H.264/H.265 Encode/Decode (up to 240 MP/s)

Ethernet:

  • Two RMII/RGMII interfaces

Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI, and
    • One QSPI

System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 23 mm x 23 mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)

Companion Power Management ICs (PMIC):

  • Functional Safety-Compliant support up to ASIL-D / SIL-3 targeted
  • Flexible mapping to support different use cases

The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview: The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview: The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance.

General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need for an external system microcontroller.
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TDA4VE-Q1 ACTIVO Sistema en un chip de automoción para estacionamiento automático y asistencia al conductor con IA, p Includes GPU, dual LPDDR4 interfaces, video encode and decode
TDA4VL-Q1 ACTIVO Sistema en chip para automoción con inteligencia artificial, gráficos para visión envolvente y aplic Includes GPU, reduced performance, smaller memory, single LPDDR4 interface, fewer MCU cores
TDA4VM-Q1 ACTIVO Sistema en chip para automoción para sistemas analíticos L2, L3 y de campo cercano mediante aprendiz Includes GPU, larger memory, integrated PCIe switch, eight-port Ethernet switch, video encode and decode accel
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NUEVO TDA4AP-Q1 PRESENTACIÓN PRELIMINAR SoC analítico automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, IA y codificador Quad Cortex-A72, 24 TOPS AI performance, three LPDDR4 interfaces, integrated Ethernet switching

Documentación técnica

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Tipo Título Fecha
* Data sheet TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0 datasheet (Rev. A) PDF | HTML 18 ago 2023
* Errata J721S2, TDA4VE, TDA4AL, TDA4VL, AM68A Processor Silicon Errata (Rev. C) PDF | HTML 24 jul 2024
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 16 nov 2024
User guide J721S2, TDA4AL, TDA4VL, TDA4VE, AM68A Technical Reference Manual (Rev. D) 24 jul 2024
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 20 jun 2024
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 04 jun 2024
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 04 abr 2024
Technical article Four power supply challenges in ADAS front camera designs PDF | HTML 05 ene 2024
Functional safety information J721E, J721S2, J7200, J784S4 MCAL TUV Certification 22 dic 2023
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. C) 11 sep 2023
User guide AM68 Power Estimation Tool User’s Guide (Rev. A) PDF | HTML 16 may 2023
User guide Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS PDF | HTML 01 mar 2023
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 09 ene 2023
User guide SK-AM68 Process Starter Kit User's Guide PDF | HTML 05 ene 2023
User guide J721S2/TDA4VE/TDA4VL/TDA4AL EVM User Guide PDF | HTML 02 dic 2022
Application note Dual-TDA4x System Solution PDF | HTML 29 abr 2022
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 05 abr 2022
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 10 ene 2022
Application note TDA4 Flashing Techniques PDF | HTML 08 jul 2021
Application note OSPI Tuning Procedure PDF | HTML 08 jul 2020

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

J721EXCPXEVM — Placa de procesador común para Jacinto™, 7 procesadores

La placa de procesador común J721EXCP01EVM para procesadores Jacinto™ 7 permite evaluar aplicaciones de visión analítica y redes en los mercados automotrices e industriales. La placa de procesador común es compatible con todos los módulos de sistema Jacinto 7 (que se venden por separado o como (...)

Guía del usuario: PDF | HTML
No disponible en TI.com
Placa de evaluación

J721S2XSOMXEVM — Sistema en módulo (SoM) TDA4VE-Q1, TDA4VL-Q1 y TDA4AL-Q1

The J721S2XSOMXEVM system on module (SoM) — when paired with the J721EXCPXEVM common processor board — is a development platform to evaluate the Jacinto™ 7 TDA4VE-Q1, TDA4VL-Q1 and TDA4AL-Q1 automotive processors for vision analytics and networking applications throughout the (...)

Guía del usuario: PDF | HTML
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Placa de evaluación

J7EXPCXEVM — Tarjeta de expansión de conmutador Gateway/Ethernet

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

Guía del usuario: PDF | HTML
No disponible en TI.com
Placa de evaluación

J7EXPEXEVM — Tarjeta de expansión de audio y pantalla

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our audio and display expansion card.
Guía del usuario: PDF | HTML
No disponible en TI.com
Placa de evaluación

PHYTC-3P-PHYCORE-AM68 — Sistema PHYTEC phyCORE-AM68 en módulo para procesadores AM68x y TDA4VE/AL/VL

El phyCORE®-AM68A se caracteriza por la integración del sistema, la escalabilidad y el ahorro de costos. El procesador combina aceleradores de aprendizaje profundo, procesamiento vectorial,  microprocesadores de uso general, así como un subsistema de imagen integrado, lo que convierte a (...)

Desde: PHYTEC
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Sonda de depuración

TMDSEMU110-U — Sonda de depuración XDS110 JTAG

El XDS110 de Texas Instruments es una nueva clase de sonda de depuración (emulador) para procesadores integrados de TI. El XDS110 sustituye a la familia XDS100, al tiempo que es compatible con una mayor variedad de estándares (IEEE1149.1, IEEE1149.7, SWD) en un único pod. Además, todas las sondas (...)

Guía del usuario: PDF
No disponible en TI.com
Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-LINUX-J721S2 — Linux® SDK for TDA4VE, TDA4VL and TDA4AL

The J721S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VL-Q1 and TDA4AL-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

(...)

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TDA4AL-Q1 — Sistema en un chip de automoción para la cámara frontal y el control del dominio ADAS mediante senso TDA4VE-Q1 — Sistema en un chip de automoción para estacionamiento automático y asistencia al conductor con IA, p TDA4VL-Q1 — Sistema en chip para automoción con inteligencia artificial, gráficos para visión envolvente y aplic
Desarrollo de hardware
Placa de evaluación
J721S2XSOMXEVM — Sistema en módulo (SoM) TDA4VE-Q1, TDA4VL-Q1 y TDA4AL-Q1
Opciones de descarga
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-QNX-J721S2 — QNX SDK for TDA4VE, TDA4VL and TDA4AL

The J721S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VL-Q1 and TDA4AL-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

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TDA4AL-Q1 — Sistema en un chip de automoción para la cámara frontal y el control del dominio ADAS mediante senso TDA4VE-Q1 — Sistema en un chip de automoción para estacionamiento automático y asistencia al conductor con IA, p TDA4VL-Q1 — Sistema en chip para automoción con inteligencia artificial, gráficos para visión envolvente y aplic
Desarrollo de hardware
Placa de evaluación
J721S2XSOMXEVM — Sistema en módulo (SoM) TDA4VE-Q1, TDA4VL-Q1 y TDA4AL-Q1
Opciones de descarga
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-RTOS-J721S2 — RTOS SDK for TDA4VE, TDA4VL and TDA4AL

The J721S2 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VL-Q1 and TDA4AL-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

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TDA4AL-Q1 — Sistema en un chip de automoción para la cámara frontal y el control del dominio ADAS mediante senso TDA4VE-Q1 — Sistema en un chip de automoción para estacionamiento automático y asistencia al conductor con IA, p TDA4VL-Q1 — Sistema en chip para automoción con inteligencia artificial, gráficos para visión envolvente y aplic
Desarrollo de hardware
Placa de evaluación
J721S2XSOMXEVM — Sistema en módulo (SoM) TDA4VE-Q1, TDA4VL-Q1 y TDA4AL-Q1
Opciones de descarga
Controlador o biblioteca

IMG-23-3-GPU-DRIVER — GPU Driver Source code from Imagination Technologies for DDK version 23.3

Required for customers and partners that require the GPU source code for custom Operating System porting
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TDA4AEN-Q1 — SoC ADAS automotriz con inteligencia artificial para aplicaciones de cámara frontal y acci TDA4AH-Q1 — SoC analítico automotriz para fusión de sensores, controladores de dominio L2, L3 con IA y codificad TDA4AL-Q1 — Sistema en un chip de automoción para la cámara frontal y el control del dominio ADAS mediante senso TDA4AP-Q1 — SoC analítico automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, IA y codificador TDA4VE-Q1 — Sistema en un chip de automoción para estacionamiento automático y asistencia al conductor con IA, p TDA4VEN-Q1 — Automotive ADAS SoC with AI, graphics, and display for entry performance park assist applications TDA4VH-Q1 — SoC automotriz para fusión de sensores, controladores de dominio L2, L3 con gráficos, IA y coprocesa TDA4VL-Q1 — Sistema en chip para automoción con inteligencia artificial, gráficos para visión envolvente y aplic TDA4VM — SoC Arm® Cortex®-A72 dual y C7x DSP con aceleradores multimedia, de visión y de aprendizaje profundo TDA4VM-Q1 — Sistema en chip para automoción para sistemas analíticos L2, L3 y de campo cercano mediante aprendiz TDA4VP-Q1 — SoC automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, gráficos, IA, coprocesador
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IDE, configuración, compilador o depurador

C7000-CGT — Herramientas de generación de código para C7000: compilador

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)
Guía del usuario: PDF | HTML
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IDE, configuración, compilador o depurador

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

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Este recurso de diseño es compatible con la mayoría de los productos de estas categorías.

Revise la página de detalles del producto para verificar la compatibilidad.
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IDE, configuración, compilador o depurador

SAFETI_CQKIT — Kit de cualificación de compilador de seguridad

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
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IDE, configuración, compilador o depurador

SYSCONFIG — Herramienta de configuración del sistema

SysConfig es una herramienta de configuración que simplifica la configuración de hardware y software y acelera el desarrollo de software.

SysConfig está disponible como parte de Code Composer Studio™, un entorno de desarrollo integrado, así como una aplicación independiente. Además, SysConfig (...)

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Sistema operativo (SO)

EB-3P-TRESOS — Software AUTOSAR Classic de Elektrobit EB Tresos

With decades of experience in the field of basic software, Elektrobit’s EB tresos product line and customized Classic AUTOSAR solutions help address each carmaker’s specific requirements delivering state-of-the-art software. For each project, Elektrobit offers the right solution to fit automotive (...)
Desde: Elektrobit
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Soporte de software

EXLFR-3P-ESYNC-OTA — Actualizaciones inalámbricas de OTA Excelfore esync para vehículos definidos por software

Experience the future of the connected SDV starting with full vehicle OTA from Excelfore. The standardized and structured eSync pipeline securely scales to reach all the ECUs and smart sensors in the car, with the flexibility to cover any in-vehicle network topology or system architecture.
eSync (...)
Desde: ExcelFore
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Soporte de software

EXLFR-3P-TSN — Rutas automotrices de la red sensible al tiempo (TSN) de ExelFore para comunicaciones críticas pa

El vehículo definido por software (SDV) necesita redes de alto rendimiento, direccionamiento IP y seguridad, que están disponibles con Ethernet pero no con red de área de controlador (CAN). Las aplicaciones automotrices también requieren características como latencias garantizadas, ancho de banda y (...)
Desde: ExcelFore
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Soporte de software

PAI-3P-PHANTOMVISION — Software de visión Phantom AI que se ejecuta en procesadores Jacinto para aplicaciones de automoción

PhantomVision™ is a scalable, flexible and reliable deep learning based computer vision solution that provides a comprehensive suite of Euro NCAP compliant ADAS features. It is a visual perception engine that enables a single or multiple cameras to autonomously recognize road objects and (...)
Desde: Phantom AI
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Modelo de simulación

AM68 TDA4VE TDA4AL TDA4VL BSDL MODEL

SPRM837.ZIP (13 KB) - BSDL Model
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Modelo de simulación

AM68A,TDA4VE,TDA4AL,TDA4VL IBIS MODEL

SPRM839.ZIP (1476 KB) - IBIS Model
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
FCBGA (ALZ) 770 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

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