Información de empaque
| Encapsulado | Pines FCBGA (ALY) | 1414 |
| Rango de temperatura de funcionamiento (℃) -40 to 125 |
| Cant. de paquetes | Empresa de transporte 1 | JEDEC TRAY (5+1) |
Características para TDA4VH-Q1
Processor cores:
- Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS
- Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz
- Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
- Depth and Motion Processing Accelerators (DMPAC)
- Eight Arm
Cortex-A72 microprocessor
subsystem at up to 2.0 GHz
- 2MB shared L2 cache per quad-core Cortex-A72 cluster
- 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
- Eight Arm
Cortex-R5F MCUs at up to 1.0
GHz
- 16K I-Cache, 16K D-Cache, 64K L2 TCM
- Two Arm Cortex-R5F MCUs in isolated MCU subsystem
- Six Arm Cortex-R5F MCUs in general compute partition
- GPU IMG BXS-4-64, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s
- Custom-designed interconnect
fabric supporting near max processing entitlement
Memory subsystem:
- Up to 8MB of on-chip L3 RAM with ECC and
coherency
- ECC error protection
- Shared coherent cache
- Supports internal DMA engine
- Up to Four External Memory Interface (EMIF)
module with ECC
- Supports LPDDR4 memory types
- Supports speeds up to 4266 MT/s
- Up to 4x32-b bus with inline ECC up to 68 GB/s
- General-Purpose Memory Controller (GPMC)
- 3x512KB on-chip SRAM in MAIN domain, protected by
ECC
Functional Safety:
-
Functional Safety-Compliant targeted (on select part
numbers)
- Developed for functional safety applications
- Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
- Systematic capability up to ASIL-D/SIL-3 targeted
- Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
- Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
- Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
- Safety-related
certification
- ISO 26262 planned
- AEC-Q100 qualilfied on part number variants
ending in Q1
Device security (on select part numbers):
- Secure boot with secure runtime support
- Customer programmable root key, up to RSA-4K or ECC-512
- Embedded hardware security module
- Crypto hardware accelerators –
PKA with ECC, AES, SHA, RNG, DES and 3DES
High speed serial interfaces:
- Integrated ethernet switch supporting up to 8
(TDA4xH) or 4 (TDA4xP) external ports
- Two ports support 5Gb, 10Gb USXGMII/XFI
- All ports support 1Gb, 2.5Gb SGMII
- All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
- Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP)
PCI-Express
(PCIe) Gen3 controllers
- Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
- One USB 3.0 dual-role device (DRD) subsystem
- Enhanced SuperSpeed Gen1 Port
- Supports Type-C switching
- Independently configurable as USB host, USB peripheral, or USB DRD
- Three CSI2.0 4L
RX plus Two CSI2.0 4L TX
Ethernet:
- Two RGMII/RMII interfaces
Automotive interfaces:
- Twenty Modular Controller Area Network (MCAN)
modules with full CAN-FD support
Display subsystem:
- Two DSI 4L TX (up to 2.5k)
- One eDP/DP interface with Multi-Display Support (MST)
- One DPI
Audio interfaces:
- Five Multichannel Audio Serial Port (MCASP)
modules
Video acceleration:
- H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH)
or 480MP/s (TDA4xP)
Flash memory interfaces:
- Embedded MultiMediaCard Interface ( eMMC™ 5.1)
- One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
- Universal Flash Storage (UFS 2.1) interface with two lanes
- Two independent flash interfaces configured as
- One OSPI or HyperBus™ or QSPI flash interfaces, and
- One QSPI flash interface
System-on-Chip (SoC) architecture:
- 16-nm FinFET technology
- 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA
(ALY), enables IPC class 3 PCB routing
TPS6594-Q1 Companion Power Management ICs (PMIC):
- Functional Safety support up to ASIL-D
- Flexible mapping to support different use cases
Descripción de TDA4VH-Q1
The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.
Key Performance Cores Overview
The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.
General Compute Cores and Integration Overview
Separate eight core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Eight Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.