Detalles del producto

Configuration 2:1 SPDT Number of channels 4 Power supply voltage - single (V) 5, 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 3.5 CON (typ) (pF) 76 ON-state leakage current (max) (µA) 0.008 Supply current (typ) (µA) 45 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic, Integrated pulldown resistor on logic pin Input/output continuous current (max) (mA) 400 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -44
Configuration 2:1 SPDT Number of channels 4 Power supply voltage - single (V) 5, 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 3.5 CON (typ) (pF) 76 ON-state leakage current (max) (µA) 0.008 Supply current (typ) (µA) 45 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic, Integrated pulldown resistor on logic pin Input/output continuous current (max) (mA) 400 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -44
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 WQFN (RRQ) 20 16 mm² 4 x 4
  • Latch-up immune
  • Dual supply range: ±4.5 V to ±22 V
  • Single supply range: 4.5 V to 44 V
  • Low on-resistance: 3 Ω
  • Low charge injection: 3 pC
  • High current support: 400 mA (maximum)
  • –40°C to +125°C operating temperature
  • 1.8 V logic compatible inputs
  • Fail-safe logic
  • Rail-to-rail operation
  • Bidirectional signal path
  • Break-before-make switching
  • Latch-up immune
  • Dual supply range: ±4.5 V to ±22 V
  • Single supply range: 4.5 V to 44 V
  • Low on-resistance: 3 Ω
  • Low charge injection: 3 pC
  • High current support: 400 mA (maximum)
  • –40°C to +125°C operating temperature
  • 1.8 V logic compatible inputs
  • Fail-safe logic
  • Rail-to-rail operation
  • Bidirectional signal path
  • Break-before-make switching

The TMUX7234 is a complementary metal-oxide semiconductor (CMOS) multiplexer with latch-up immunity. The TMUX7234 contains four independently controlled SPDT switches with an EN pin to enable or disable all four channels. The device supports single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7234 supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.

All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.

The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments.

The TMUX7234 is a complementary metal-oxide semiconductor (CMOS) multiplexer with latch-up immunity. The TMUX7234 contains four independently controlled SPDT switches with an EN pin to enable or disable all four channels. The device supports single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7234 supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.

All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.

The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments.

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Documentación técnica

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Tipo Título Fecha
* Data sheet TMUX7234 44 V, Low Ron, 2:1, 4 Channel Precision Switches with Latch-Up Immunity and 1.8 V Logic datasheet (Rev. G) PDF | HTML 18 jul 2024
Application note How to Handle High Voltage Common Mode Applications using Multiplexers PDF | HTML 03 oct 2022
Application note Using Latch Up Immune Multiplexers to Help Improve System Reliability (Rev. A) 20 sep 2021
Application brief Precision Multiplexers Reducing Barriers in an Industrial Environment PDF | HTML 21 may 2021

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

TMUXRTJ-RRQEVM — Módulo de evaluación de TMUX genérico para paquetes RRQ QFN y RTJ de 20 pines

El TMUXRTJ-RRQEVM permite la rápida creación de prototipos y la caracterización de CC de la línea de productos TMUX de TI que utilizan encapsulados RTJ o RRQ (QFN) de 20 pines y está preparado para funcionar a alta tensión.

Guía del usuario: PDF | HTML
Adaptador de interfaz

LEADED-ADAPTER1 — Adaptador de montaje superficial a conector macho DIP para pruebas rápidas de encapsulados con plomo

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Guía del usuario: PDF
Adaptador de interfaz

LEADLESS-ADAPTER1 — Adaptador de montaje superficial a conector macho DIP para pruebas de encapsulados sin plomo de 6, 8

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
Guía del usuario: PDF
Modelo de simulación

TMUX7234 IBIS Model

SCDM264.ZIP (52 KB) - IBIS Model
Modelo de simulación

TMUX72XX-8SW - TMUX723X PSPICE Model

SCDM303.ZIP (29 KB) - PSpice Model
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
TSSOP (PW) 20 Ultra Librarian
WQFN (RRQ) 20 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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