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Gestión de la energía
Controladores de compuertas
Drivers de compuerta aislados

UCC21222

ACTIVO

Controlador de puerta aislada de doble canal (4 A/6 A) y 3.0 kVrms, con pin de desactivación, tiempo

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NUEVO UCC21330 ACTIVO 3kVRMS 4A/6A two-channel isolated gate driver with disable logic and programmable deadtime Improved CMTI, faster VDD startup

UCC21222

ACTIVO
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Detalles del producto

Number of channels 2 Isolation rating Basic Withstand isolation voltage (VISO) (Vrms) 3000 Working isolation voltage (VIOWM) (Vrms) 990 Transient isolation voltage (VIOTM) (VPK) 4242 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 6 Features Disable, Programmable dead time Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 9.2 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 990 Rise time (ns) 5 Fall time (ns) 6 Undervoltage lockout (typ) (V) 8
Number of channels 2 Isolation rating Basic Withstand isolation voltage (VISO) (Vrms) 3000 Working isolation voltage (VIOWM) (Vrms) 990 Transient isolation voltage (VIOTM) (VPK) 4242 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 6 Features Disable, Programmable dead time Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 9.2 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 990 Rise time (ns) 5 Fall time (ns) 6 Undervoltage lockout (typ) (V) 8
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Resistor-programmable dead time
  • Universal: dual low-side, dual high-side or half-bridge driver
  • 4A peak source, 6A peak sink output
  • 3V to 5.5V input VCCI range
  • Up to 18V VDD output drive supply
    • 8V VDD UVLO
  • Switching parameters:
    • 28ns typical propagation delay
    • 10ns minimum pulse width
    • 5ns maximum delay matching
    • 5.5ns maximum pulse-width distortion
  • TTL and CMOS compatible inputs
  • Integrated deglitch filter
  • I/Os withstand –2V for 200ns
  • Common-mode transient immunity (CMTI) greater than 100V/ns
  • Isolation barrier life >40 Years
  • Surge immunity up to 7800VPK
  • Narrow body SOIC-16 (D) package
  • Safety-related certifications (planned):
    • 4242VPK isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
    • 3000VRMS isolation for 1 minute per UL 1577
    • CSA certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 end equipment standards
    • CQC Certification per GB4943.1-2011
  • Create a Custom Design Using the UCC21222 With the WEBENCH® Power Designer
  • Resistor-programmable dead time
  • Universal: dual low-side, dual high-side or half-bridge driver
  • 4A peak source, 6A peak sink output
  • 3V to 5.5V input VCCI range
  • Up to 18V VDD output drive supply
    • 8V VDD UVLO
  • Switching parameters:
    • 28ns typical propagation delay
    • 10ns minimum pulse width
    • 5ns maximum delay matching
    • 5.5ns maximum pulse-width distortion
  • TTL and CMOS compatible inputs
  • Integrated deglitch filter
  • I/Os withstand –2V for 200ns
  • Common-mode transient immunity (CMTI) greater than 100V/ns
  • Isolation barrier life >40 Years
  • Surge immunity up to 7800VPK
  • Narrow body SOIC-16 (D) package
  • Safety-related certifications (planned):
    • 4242VPK isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
    • 3000VRMS isolation for 1 minute per UL 1577
    • CSA certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 end equipment standards
    • CQC Certification per GB4943.1-2011
  • Create a Custom Design Using the UCC21222 With the WEBENCH® Power Designer

The UCC21222 device is an isolated dual channel gate driver with programmable dead time. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.

The device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. A 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.

The input side is isolated from the two output drivers by a 3.0kVRMS isolation barrier, with a minimum of 100V/ns common-mode transient immunity (CMTI).

Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include a disable feature to shut down both outputs simultaneously when DIS is set high, an integrated deglitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection.

The UCC21222 device is an isolated dual channel gate driver with programmable dead time. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.

The device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. A 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.

The input side is isolated from the two output drivers by a 3.0kVRMS isolation barrier, with a minimum of 100V/ns common-mode transient immunity (CMTI).

Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include a disable feature to shut down both outputs simultaneously when DIS is set high, an integrated deglitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection.
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Documentación técnica

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* Data sheet UCC21222 4A, 6A, 3.0kVRMS Isolated Dual-Channel Gate Driver with Dead Time datasheet (Rev. B) PDF | HTML 05 feb 2024
Certificate VDE Certificate for Basic Isolation for DIN EN IEC 60747-17 (Rev. W) 31 ene 2024
Certificate UCC21220 CQC Certificate of Product Certification 16 ago 2023
Application brief The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML 16 dic 2021
Certificate FPPT2 - Nonoptical Isolating Devices UL 1577 Certificate of Compliance 26 oct 2021
Test report Peak Efficiency at 99%, 585-W High-Voltage Buck Reference Design 24 abr 2020
Application brief External Gate Resistor Selection Guide (Rev. A) 28 feb 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28 feb 2020
Certificate UL Certification E181974 Vol 4. Sec 9 (Rev. A) 22 jul 2019
User guide Gate Drive Voltage vs. Efficiency 25 abr 2019
Application brief How to Drive High Voltage GaN FETs with UCC21220A 06 mar 2019
White paper Impact of an isolated gate driver (Rev. A) 20 feb 2019
Application note Common Mode Transient Immunity (CMTI) for UCC2122x Isolated Gate Drivers 19 jul 2018
White paper Demystifying high-voltage power electronics for solar inverters 06 jun 2018
Application note Solar Inverter Layout Considerations for UCC21220 06 jun 2018
Technical article Boosting efficiency for your solar inverter designs PDF | HTML 24 may 2018

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

UCC21220EVM-009 — Módulo de evaluación UCC21220 de controlador de puerta aislada de doble canal (4 A y 6 A) y 3.0 kVrm

UCC21220EVM-009 is designed for evaluating UCC21220, which is a 3.0-kVRMS Isolated Dual-Channel Gate Driver with 4.0-A source and 6.0-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component selection (...)
Guía del usuario: PDF
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Modelo de simulación

UCC21222-Q1 PSpice Transient Model

SLUM622.ZIP (57 KB) - PSpice Model
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Modelo de simulación

UCC21222-Q1 Unencrypted PSpice Transient Model

SLUM623.ZIP (3 KB) - PSpice Model
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Herramienta de cálculo

SLURAZ5 — UCC21520 Bootstrap Calculator 1.0

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Drivers de compuerta aislados
UCC21220 — Controlador de puerta aislada de doble canal (4 A/6 A) y 3.0 kVrms, con pin de desactivación y UVLO UCC21222 — Controlador de puerta aislada de doble canal (4 A/6 A) y 3.0 kVrms, con pin de desactivación, tiempo UCC21520 — Controlador de puerta aislada de doble canal (4 A/6 A) y 5.7 kVrms con entrada doble, pin de desacti UCC21521 — Controlador de puerta aislada de doble canal (4 A/6 A) y 5.7 kVrms con entrada doble, activación
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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Diseños de referencia

PMP41006 — Diseño de referencia de PFC de polo tótem CCM de 1 kW y LLC con modo de corriente proporcionado por

Este diseño de referencia demuestra un método de control de histéresis híbrido (HHC), un tipo de método de control de modo actual en una etapa LLC de medio puente con un microcontrolador C2000™ F28004x. El hardware se basa en TIDA-010062, que es un diseño de referencia LLC de medio puente y (...)
Test report: PDF
Diseños de referencia

TIDA-010203 — Diseño de referencia PFC de polo tótem monofásico de 4 kW con C2000 y GaN

This reference design is a 4-kW CCM totem-pole PFC with F280049/F280025 control card and LMG342x EVM board. This design demos a robust PFC solution, which avoids isolated current sense by putting the controller's ground in the middle of a MOSFET leg. Benefitting from non-isolation, AC current (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

PMP41043 — Diseño de referencia de PFC de polo tótem CCM de 1.6 kW y LLC con modo de corriente proporcionado po

Este diseño de referencia demuestra un método de control de histéresis híbrido (HHC), un método de control de modo actual en una etapa LLC de medio puente con un microcontrolador C2000™ F28004x. El hardware se basa en TIDA-010062, que es un diseño de referencia LLC de medio puente y titanio 80-Plus (...)
Test report: PDF
Diseños de referencia

PMP40500 — Diseño de referencia de medio puente de 54 VCC de entrada y 12 V 42 A de salida<

This 12-V, 42-A output half-bridge reference design is for bus converters in wired networking campus and branch switches. The design features high efficiency and various fault protections (over-current and short-circuit). The design provides an efficiency comparison using 3 kVRMS basic and (...)
Test report: PDF
Esquema: PDF
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SOIC (D) 16 Ultra Librarian
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Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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Soporte y capacitación

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