CD74HCT646

Name: CD74HCT646
Brand: TI
SKU: CD74HCT646
Price: 1.139 USD

アクティブ

ハイスピード CMOS ロジック、3 ステート出力、非反転型、オクタル・バス・トランシーバ / レジスタ

ご注文はこちら

データシート

document-pdfAcrobat CD54HC646, CD74HCT646 データシート (Rev. B) (英語)

CD74HCT646

アクティブ

データシート

ご注文はこちら

製品詳細

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

8

IOL (max) (mA)

6

IOH (max) (mA)

-6

Input type

TTL

Output type

3-State

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Technology family

HCT

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

8

IOL (max) (mA)

6

IOH (max) (mA)

-6

Input type

TTL

Output type

3-State

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Technology family

HCT

Rating

Catalog

Operating temperature range (°C)

-55 to 125

SOIC (DW)

24

159.65 mm² 15.5 x 10.3

2-V to 6-V V_CC Operation (CD54HC646)
4.5-V to 5.5-V V_CC Operation (CD74HCT646)
Wide Operating Temperature Range of –55°C to 125°C
Balanced Propagation Delays and Transition Times
Standard Outputs Drive Up To 15 LS-TTL Loads
Significant Power Reduction Compared to LS-TTL Logic ICs
Inputs Are TTL-Voltage Compatible (CD74HCT646)
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
True Data Paths

2-V to 6-V V_CC Operation (CD54HC646)
4.5-V to 5.5-V V_CC Operation (CD74HCT646)
Wide Operating Temperature Range of –55°C to 125°C
Balanced Propagation Delays and Transition Times
Standard Outputs Drive Up To 15 LS-TTL Loads
Significant Power Reduction Compared to LS-TTL Logic ICs
Inputs Are TTL-Voltage Compatible (CD74HCT646)
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
True Data Paths

The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.

Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices.

Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\ is active (low). In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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