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CDC2510C

新規設計での使用を推奨しません

PC SDRAM レジスタード DIMM 設計サポート資料 rev. 1.2 (PC SDRAM registered DIMM design support document rev. 1.2) に

ご注文はこちら
データシート
CDC2510C は新規設計での使用を推奨しません
これまでにご購入されたお客様をサポートする目的でこの製品を引き続き生産しています。新規設計では代替品をご検討ください。
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CDCVF2510 アクティブ DRAM アプリケーション向け、10 出力、3.3V、フェーズ・ロック・ループ・クロック・ドライバ Can achieve better performance

CDC2510C

新規設計での使用を推奨しません
データシート ご注文はこちら

製品詳細

Function Zero-delay Output frequency (max) (MHz) 125 Number of outputs 10 Core supply voltage (V) 3.3 Output skew (ps) 250 Operating temperature range (°C) to Rating Catalog
Function Zero-delay Output frequency (max) (MHz) 125 Number of outputs 10 Core supply voltage (V) 3.3 Output skew (ps) 250 Operating temperature range (°C) to Rating Catalog
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Use CDCVF2510A as a Replacement for this Device
  • Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2
  • Spread Spectrum Clock Compatible
  • Operating Frequency 25 MHz to 125 MHz
  • Static tPhase Error Distribution at 66 MHz to 100 MHz is ±150 ps
  • Drop-In Replacement for TI CDC2510A With Enhanced Performance
  • Jitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Ten Outputs
  • External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V
  • Use CDCVF2510A as a Replacement for this Device
  • Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2
  • Spread Spectrum Clock Compatible
  • Operating Frequency 25 MHz to 125 MHz
  • Static tPhase Error Distribution at 66 MHz to 100 MHz is ±150 ps
  • Drop-In Replacement for TI CDC2510A With Enhanced Performance
  • Jitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Ten Outputs
  • External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC2510C is characterized for operation from 0°C to 85°C.

For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039).

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC2510C is characterized for operation from 0°C to 85°C.

For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039).
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート CDC2510C: 3.3-V Phase-Lock Loop Clock Driver データシート (Rev. A) 2004年 12月 2日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
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