CDCVF2510A
- Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
- Spread Spectrum Clock Compatible
- Operating Frequency 20 MHz to 175 MHz
- Static Phase Error Distribution at 66 MHz to 166 MHz is ±125 ps
- Jitter (cyc–cyc) at 66 MHz to 166 MHz is |70| ps
- Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption vs Current Generation PC133 Devices
- Auto Frequency Detection to Disable Device (Power-Down Mode)
- Available in Plastic 24-Pin TSSOP
- Distributes One Clock Input to One Bank of 10 Outputs
- External Feedback (FBIN) Terminal is Used to Synchronize the Outputs to the Clock Input
- 25-
On-Chip Series Damping Resistors - No External RC Network Required
- Operates at 3.3 V
- APPLICATIONS
- DRAM Applications
- PLL Based Clock Distributors
- Non-PLL Clock Buffer
The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510A operates at a 3.3-V VCC and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. The device automically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a low state.
Unlike many products containing PLLs, the CDCVF2510A does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCVF2510A requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground to use as a simple clock buffer.
The CDCVF2510A is characterized for operation from 0°C to 85°C.
技術資料
| 種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
|---|---|---|---|---|---|---|
| * | データシート | 3.3-V Phase-Lock Loop Clock Driver データシート (Rev. C) | 2009年 2月 9日 | |||
| その他の技術資料 | クロック＆タイミング・ソリューション (Rev. A 翻訳版) | 2013年 12月 11日 | ||||
| アプリケーション・ノート | Generating Early Clock using TI's CDCVF2509/CDCVF2510 PLLs | 2004年 7月 23日 |
設計および開発
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| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| TSSOP (PW) | 24 | Ultra Librarian |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点
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