SN74BCT29854
- BiCMOS Process With TTL Inputs and Outputs
- State-of-the-Art BiCMOS Design Significantly Reduces Standby Current
- Flow-Through Pinout (All Inputs on Opposite Side From Outputs)
- Functionally Equivalent to AMD Am29854
- High-Speed Bus Transceiver With Parity Generator/Checker
- Parity-Error Flag With Open-Collector Output
- Latch for Storage of the Parity-Error Flag
- Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)
The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed
for asynchronous communication between data buses. When data is
transmitted from the A to B bus, a parity bit is generated. When data
is transmitted from the B to A bus with its corresponding parity bit,
the parity-error (
) output will
indicate whether or not an error in the B data has occurred. The
output-enable (
, 
) inputs can be used to disable the
device so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY)
output and monitors the parity of the I/O ports with an
open-collector parity-error () flag. can
be either passed, sampled, stored, or cleared from the latch using
the latch-enable (
) and clear
(
) control
inputs. When both and are low, data is transferred from
the A bus to the B bus and inverted parity is generated. Inverted
parity is a forced error condition which gives the designer more
system diagnostic capability. The SN74BCT29854 provides inverting
logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
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技術資料
| 種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
|---|---|---|---|---|---|---|
| * | データシート | 8-Bit To 9-Bit Parity Bus Transceiver データシート | 1993年 11月 1日 |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点