SN74HC193-Q1

Name: SN74HC193-Q1
Brand: TI
SKU: SN74HC193-Q1
Price: 0.271 USD

アクティブ

車載カタログ、4 ビット非同期アップ / ダウン・カウンタ (デュアル・クロックとクリア搭載)

ご注文はこちら

データシート

document-pdfAcrobat 4-Bit Synchronous Up/Down Counter データシート (Rev. A) (英語)

SN74HC193-Q1

アクティブ

データシート

ご注文はこちら

製品詳細

Function

Counter

Bits (#)

4

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Function

Counter

Bits (#)

4

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

TSSOP (PW)

16

32 mm² 5 x 6.4

Qualified for Automotive Applications
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I_CC
Typical t_pd = 20 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Look-Ahead Circuitry Enhances Cascaded Counters
Fully Synchronous in Count Modes
Parallel Asynchronous Load for Modulo-N Count Lengths
Asynchronous Clear

Qualified for Automotive Applications
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I_CC
Typical t_pd = 20 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Look-Ahead Circuitry Enhances Cascaded Counters
Fully Synchronous in Count Modes
Parallel Asynchronous Load for Modulo-N Count Lengths
Asynchronous Clear

The SN74HC193 device is a 4-bit synchronous, reversible, up/down binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously with each other when dictated by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.

The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP or DOWN). The direction of counting is determined by which count input is pulsed while the other count input is high.

All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs.

A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and LOAD inputs.

This counter was designed to be cascaded without the need for external circuitry. The borrow (BO) output produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO) output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counter then can be cascaded easily by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter.

The SN74HC193 device is a 4-bit synchronous, reversible, up/down binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously with each other when dictated by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.

The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP or DOWN). The direction of counting is determined by which count input is pulsed while the other count input is high.

All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs.

A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and LOAD inputs.

This counter was designed to be cascaded without the need for external circuitry. The borrow (BO) output produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO) output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counter then can be cascaded easily by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter.

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