TXG1041
- Supports DC shifts up to ±10V
- AC Noise Rejection of 20VPP up to 45MHz
- CMTI of 1kV/µs
- Low Prop Delay (<5ns) and Ch-Ch Skew (0.35ns)
- Greater than 250Mbps
- Low power consumption (0.65mA per channel at 1Mbps, 1.8V)
- Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
- 4, 2, 1 channel devices with multiple configurations will be available
- Two device variants:
- TXG1041: 3 forward, 1 reverse
- TXG1042: 2 forward, 2 reverse
- Supports VCC disconnect feature (I/Os are forced into high-Z)
- Schmitt-trigger inputs allows for slow and noisy signals
- Inputs with integrated static pull-down resistors prevent channels from floating
- Operating temperature from –40°C to +125°C
- Latch-up performance exceeds 100mA per JESD 78, class II
- ESD protection exceeds JESD 22
- 4000V human-body model
- 500V charged-device model
- Package options provided:
- RUC (X2QFN-14)
- DYY (SOT-14)
- DBQ (QSOP-16)
The TXG104x is a 4-bit, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±10V. Compared to traditional level shifters, the TXG104x family can solve the challenges of voltage translation across different ground levels. The Figure 1-1 shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.
VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. This device includes two enable pins that can place the respective outputs in a high-impedance state when the OE pin is connected to GND or left floating. In the event of input power or signal loss, the output is default low when OE is High (refer to ). The leakage between GNDA and GNDB is <30nA when VCC to GND is shorted.
The TXG104x device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can supress noise levels of 20VPP up to 45MHz (Figure 7-4). This device can support multiple interfaces such as SPI, UART, GPIO, and I2S.
技術資料
設計および開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
---|---|---|
SSOP (DBQ) | 16 | Ultra Librarian |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点