封裝資訊
| 封裝 | 針腳 CCGA (NAA) | 376 |
| 操作溫度範圍 (°C) -55 to 125 |
| 包裝數量 | 運送業者 144 | EIAJ TRAY (10+1) |
ADC10D1000QML-SP 的特色
- Total Ionizing Dose 100 krad(Si)
- Single Event Latch-Up 120 Mev-cm2/mg
- Excellent Accuracy and Dynamic Performance
- Low Power Consumption
- R/W SPI Interface for Extended Control Mode
- Internally Terminated, Buffered, Differential Analog Inputs
- Ability to Interleave the 2 Channels to Operate 1 Channel at Twice the Conversion Rate
- Test Patterns at Output for System Debug
- Programmable 15-Bit Gain and 12-Bit Plus Sign Offset Adjustments
- Option of 1:2 Demuxed or 1:1 Non-demuxed LVDS Outputs
- Auto-sync Feature for Multi-chip Systems
- Single 1.9 ±0.1-V Power Supply
- 376 Ceramic Pin Grid Array Package (28.2 mm x 28.2 mm x 3.1 mm with 1.27 mm ball-pitch)
ADC10D1000QML-SP 的說明
The ADC10D1000 is the latest advance in TI's Ultra-High-Speed ADC family of products. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution at sampling rates of up to 1.0 GSPS in dual channel mode or 2.0 GSPS in single channel mode. The ADC10D1000 achieves excellent accuracy and dynamic performance while consuming a typical 2.9 W of power. This space grade, Radiation Tolerant part is rad hard to a single event latch up level of greater than 120MeV and a total dose (TID) of 100 krad(Si). The product is packaged in a hermatic 376 column thermally enhanced CPGA package rated over the temperature range of -55°C to +125°C.
The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. New features include an auto-sync feature for multi-chip synchronization, independent programmable15-bit gain and 12-bit offset adjustment per channel, LC tank filter on the clock input, and the option of two's complement format for the digital output data. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal track-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 8.9 Effective Number of Bits (ENOB) with a 498 MHz input signal and a 1.0 GHz sample rate while providing a 10−18 Code Error Rate (C.E.R.) Consuming a typical 2.9 W in Non-Demultiplex Mode at 1.0 GSPS from a single 1.9-V supply, this device is ensured to have no missing codes over the full operating temperature range.
Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demultiplexed Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower, but two times wider to relax data-capture timing margin. The two channels (I and Q) can also be interleaved (DES Mode) and used as a single 2.0 GSPS ADC to sample on the Q input. The output formatting is offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8 V and 1.2 V.