首頁 邏輯和電壓轉換 正反器、鎖存器和暫存器 D 型正反器
首頁
邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型正反器

CD54HCT175

現行

具有重設功能的高速 CMOS 邏輯四路 D 型正反器

立即訂購
產品規格表

CD54HCT175

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 4 Technology family HCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 16 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 4 Technology family HCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 16 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Common Clock and Asynchronous Reset on Four D-Type Flip-Flops
  • Positive Edge Pulse Triggering
  • Complementary Outputs
  • Buffered Inputs
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH
  • Common Clock and Asynchronous Reset on Four D-Type Flip-Flops
  • Positive Edge Pulse Triggering
  • Complementary Outputs
  • Buffered Inputs
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

The ’HC175 and ’HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.

Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1.

The ’HC175 and ’HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.

Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1.
filter 尋找其它 D 型正反器
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 14
類型 標題 日期
* Data sheet CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 datasheet (Rev. C) 2003年 10月 13日
* SMD CD54HCT175 SMD 5962-89701 2016年 6月 21日
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996年 5月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

封裝 針腳 CAD 符號、佔位空間與 3D 模型
CDIP (J) 16 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片