CD74HC191

Name: CD74HC191
Brand: TI
SKU: CD74HC191
Price: 0.276 USD

現行

高速 CMOS 邏輯可預設的同步 4 位元二進位加/減計數器

立即訂購

產品規格表

document-pdfAcrobat CD54HC190, CD74HC190, CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 datasheet (Rev. E) (英文)

CD74HC191

現行

產品規格表

立即訂購

產品詳細資料

Function

Counter

Bits (#)

4

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Function

Counter

Bits (#)

4

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

2-V to 6-V V_CC Operation (’HC190,191)
4.5-V to 5.5-V V_CC Operation (’HCT191)
Wide Operating Temperature Range of –55 to 125°C
Synchronous Counting and Asynchronous Loading
Two Outputs for n-Bit Cascading
Look-Ahead Carry for High-Speed Counting
Balanced Propagation Delay and Transition Times
Standard Outputs Drive Up To 15 LS-TTL Loads
Significant Power Reduction Compared to LS-TTL Logic ICs

2-V to 6-V V_CC Operation (’HC190,191)
4.5-V to 5.5-V V_CC Operation (’HCT191)
Wide Operating Temperature Range of –55 to 125°C
Synchronous Counting and Asynchronous Loading
Two Outputs for n-Bit Cascading
Look-Ahead Carry for High-Speed Counting
Balanced Propagation Delay and Transition Times
Standard Outputs Drive Up To 15 LS-TTL Loads
Significant Power Reduction Compared to LS-TTL Logic ICs

The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.

Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.

When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).

If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).

The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.

Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.

When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).

If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).

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