首頁 時鐘與計時 時鐘緩衝器
首頁
時鐘與計時
時鐘緩衝器

CDCM1802

現行

具有可編程分頻器、LVPECL I/O 和 LVCMOS 輸出時鐘緩衝器

立即訂購
產品規格表

CDCM1802

現行
產品規格表 立即訂購

產品詳細資料

Function Clock divider, Fanout Additive RMS jitter (typ) (fs) 150 Output frequency (max) (MHz) 800 Number of outputs 1 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 1600 Features Pin programmable Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS, LVPECL Input type LVPECL
Function Clock divider, Fanout Additive RMS jitter (typ) (fs) 150 Output frequency (max) (MHz) 800 Number of outputs 1 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 1600 Features Pin programmable Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS, LVPECL Input type LVPECL
VQFN (RGT) 16 9 mm² 3 x 3
  • Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output
  • Programmable Output Divider for Both LVPECL and LVCMOS Outputs
  • 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
  • 3.3-V Power Supply (2.5-V Functional)
  • Signaling Rate Up to 800-MHz LVPECL and
    200-MHz LVCMOS
  • Differential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 16-Pin VQFN Package (3.00 mm × 3.00 mm)
  • Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output
  • Programmable Output Divider for Both LVPECL and LVCMOS Outputs
  • 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
  • 3.3-V Power Supply (2.5-V Functional)
  • Signaling Rate Up to 800-MHz LVPECL and
    200-MHz LVCMOS
  • Differential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals
  • Receiver Input Threshold ±75 mV
  • 16-Pin VQFN Package (3.00 mm × 3.00 mm)

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.

filter 尋找其它 時鐘緩衝器
下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
功能相似於所比較的產品
CDCM1804 現行 1:3 LVPECL 時鐘緩衝器和 LVCMOS 輸出及可編程分頻器 1:4 LVPECL buffer divider
CDCP1803 現行 具有可編程分頻器的 1:3 LVPECL 時鐘緩衝器 1:3 LVPECL buffer divider
LMK01000 現行 具 3 個 LVDS 和 5 個 LVPECL 輸出的 1.6-GHz 高性能時脈緩衝器、分頻器和分配器 1:8, LVPECL/LVDS buffer divider

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 3
類型 標題 日期
* Data sheet CDCM1802 Clock Buffer With Programmable Divider, LVPECL I/O + Additional LVCMOS Output datasheet (Rev. C) PDF | HTML 2017年 7月 6日
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 2024年 4月 30日
Application note CDCM1802/CDCM1804 2004年 8月 4日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

CDCM1802 IBIS Model

SCAC051.ZIP (25 KB) - IBIS Model
下載
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGT) 16 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片