CDCM61004
- One Crystal/LVCMOS Reference Input
Including 24.8832 MHz, 25 MHz, and 26.5625 MHz - Input Frequency Range: 21.875 MHz to
28.47 MHz - On-Chip VCO Operates in Frequency Range of
1.75 GHz to 2.05 GHz - 4x Output Available:
- Pin-Selectable Between LVPECL, LVDS, or
2-LVCMOS; Operates at 3.3 V
- Pin-Selectable Between LVPECL, LVDS, or
- LVCMOS Bypass Output Available
- Output Frequency Selectable by /1, /2, /3, /4, /6,
/8 from a Single Output Divider - Supports Common LVPECL/LVDS Output
Frequencies:- 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
155.52 MHz, 156.25 MHz, 159.375 MHz,
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,
311.04 MHz, 312.5 MHz, 622.08 MHz,
625 MHz
- 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
- Supports Common LVCMOS Output Frequencies:
- 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
155.52 MHz, 156.25 MHz, 159.375 MHz,
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz
- 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
- Output Frequency Range: 43.75 MHz to
683.264 MHz - Internal PLL Loop Bandwidth: 400 kHz
- High-Performance PLL Core:
- Phase Noise typically at –146 dBc/Hz at
5-MHz Offset for 625-MHz LVPECL Output - Random Jitter typically at 0.509 ps, RMS
(10 kHz to 20 MHz) for 625-MHz LVPECL Output
- Phase Noise typically at –146 dBc/Hz at
- Output Duty Cycle Corrected to 50% (± 5%)
- Low Output Skew of 30 ps on LVPECL Outputs
- Divider Programming Using Control Pins:
- Two Pins for Prescaler/Feedback Divider
- Three Pins for Output Divider
- Two Pins for Output Select
- Chip Enable Control Pin Available
- 3.3-V Core and I/O Power Supply
- Industrial Temperature Range: –40°C to 85°C
- 5-mm × 5-mm, 32-pin, VQFN (RHB) Package
- ESD Protection Exceeds 2 kV (HBM)
The CDCM61004 is a highly versatile, low-jitter frequency synthesizer capable of generating four low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal of LVCMOS input for a variety of wireline and data communication applications. The CDCM61004 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1 ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61004 is available in a small, 32-pin, 5-mm × 5-mm VQFN package.
The CDCM61004 is a high-performance, low-phase noise, fully-integrated voltage-controlled
oscillator (VCO) clock synthesizer with four universal output buffers that can be configured to be
LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS
outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which
can help with crystal loading to achieve an exact desired input frequency. It has one
fully-integrated, low-noise, LC-based VCO that operates in the
1.75 GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output share an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividers are turned off.
The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUT with respect to fIN.
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins. CDCM61004 Block Diagram shows a high-level diagram of the CDCM61004.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCM61004 Four Output, Integrated VCO, Low-Jitter Clock Generator datasheet (Rev. H) | PDF | HTML | 2016年 1月 13日 |
| White paper | Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) | PDF | HTML | 2024年 4月 30日 | |
| User guide | Low Phase Noise Clock Evaluation Module (Rev. B) | 2011年 3月 2日 | ||
| Application note | Using LVCMOS Input to the CDCM6100x | 2010年 5月 23日 | ||
| Analog Design Journal | TI Powers Altera's Arria II GX FPGA Development Kit | 2009年 9月 29日 | ||
| Application note | Ethernet Clock Generation Using the CDCM6100x | 2009年 2月 18日 | ||
| Application note | Fibre Channel and SAN Clock Generation Using the CDCM6100x | 2009年 2月 18日 |
設計與開發
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CDCM6100XEVM — CDCM61004/CDCM61002/CDCM61001 評估模組
CDCM6100xEVM is the evaluation module for CDCM61004 or CDCM61002 or CDCM61001. CDCM61004/2/1 family is a highly versatile, ultra low-jitter frequency synthesizer family that can generate four/two/one low-jitter clock output pairs, selectable among LVPECL, LVDS, or 2 LVCMOS, from a low-frequency (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHB) | 32 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。