CDCVF111
- Low-Output Skew for Clock-Distribution Applications
- Differential Low-Voltage Pseudo-ECL (LVPECL) Compatible Inputs and Outputs
- Distributes Differential Clock Inputs to Nine Differential Clock Outputs
- Output Reference Voltage (VREF) Allows Distribution From a Single-Ended Clock Input
- Packaged In a 28-Pin Plastic Chip Carrier
The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN)\ to nine pairs of differential clock (Y, Y)\ outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.
The VREF output can be strapped to the CLKIN\ input for a single-ended CLKIN input.
The CDCVF111 is characterized for operation from 40°C to 85°C.
技術文件
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檢視所有 1 類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 1:9 Differential LVPECL Clock Driver datasheet (Rev. B) | 2002年 6月 7日 |
訂購與品質
內含資訊:
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊:
- 晶圓廠位置
- 組裝地點