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移位暫存器

CY29FCT520T

現行

8 位元多級管道暫存器

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產品規格表

CY29FCT520T

現行
產品規格表 立即訂購

產品詳細資料

Configuration Universal Bits (#) 8 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features High speed (tpd 10-50ns), Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
Configuration Universal Bits (#) 8 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features High speed (tpd 10-50ns), Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Single- and Dual-Pipeline Operation Modes
  • Multiplexed Data Inputs and Outputs
  • CY29FCT520T
    • 64-mA Output Sink Current
      32-mA Output Source Current
  • CY29FCT520ATDMB, CY29FCT520BTDMB
    • 32-mA Output Sink Current
      12-mA Output Source Current
  • 3-State Outputs
  • Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Single- and Dual-Pipeline Operation Modes
  • Multiplexed Data Inputs and Outputs
  • CY29FCT520T
    • 64-mA Output Sink Current
      32-mA Output Source Current
  • CY29FCT520ATDMB, CY29FCT520BTDMB
    • 32-mA Output Sink Current
      12-mA Output Source Current
  • 3-State Outputs

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1).

The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.

In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1).

The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.

In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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其他裝置和產品規格表

本產品規格表適用於 CY29FCT520T 和 CY29FCT520T-MIL

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技術文件

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類型 標題 日期
* Data sheet Multilevel Pipeline Register With 3-State Outputs datasheet (Rev. C) 2001年 11月 2日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
User guide CYFCT Parameter Measurement Information 2001年 4月 2日
Selection guide Advanced Bus Interface Logic Selection Guide 2001年 1月 9日

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