引腳對引腳且具備與所比較裝置相同的功能
CY74FCT16823T
- Ioff supports partial-power-down mode operation
- Edge-rate control circuitry for significantly improved noise characteristics
- Typical output skew < 250 ps
- ESD > 2000V
- TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages
- Industrial temperature range of -40°C to +85°C
- VCC = 5V ± 10%
- CY74FCT16823T Features:
- 64 mA sink current, 32 mA source current
- Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25°C
- CY74FCT162823T Features:
- Balanced 24 mA output drivers
- Reduced system switching noise
- Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA = 25°C
The CY74FCT16823T and the CY74FCT162823T 18-bit bus interface registers are designed for use in high-speed, low-power systems needing wide registers and parity. 18-bit operation is achieved by connecting the control lines of the two 9-bit registers. Flow-through pinout and small shrink packaging aids in simplifying board layout.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The CY74FCT16823T is ideally suited for driving high-capacitance loads and low-impedance backplanes.
The CY74FCT162823T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162823T is ideal for driving transmission lines.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 18-Bit Registers datasheet (Rev. B) | 2001年 9月 19日 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點