DAC39RFS10EF
- 10.24/20.48GSPS, multi-Nyquist DAC Cores
- Maximum input data rate vs DAC resolution:
- 16-bit: 1.22GSPS complex
- 11-bit: 3.41GSPS complex
- 9-bit, Single channel, DES mode: 15.12GSPS
- 8-bit, Single channel, DES mode: 20.48GSPS
- 9-bit, Dual channel: 7.56GSPS/ch
- 8-bit, Dual channel, 10.24GSPS/ch
- Output bandwidth (–3dB): 12GHz
- Performance at fOUT = 2.997 GHz, DES2XL mode, DEM/Dither on
- Noise floor (small signal): –150dBFS/Hz
- SFDR (–0.1dBFS) : 77dBc
- IMD3 (–7dBFS each tone) : –69dBc
- Four Integrated digital up-converters (DUC)
- Interpolation: 1x, 2x, 3x, 4x, 6x, 8x, 12x ... 256x
- Complex baseband DUC for I/Q output
- Complex to real up conversion for dual channel direct RF sampling
- 64-bit frequency resolution NCOs
- Fast reconfiguration interface for fast frequency hopping
- 4-bit data with 200MHz clock
- 60 ns reconfiguration (32-bit frequency)
- Any frequency hopping with phase coherence
- JESD204C Interface
- Up to 16 Lanes at up to 12.8Gbps
- Class C-S, subclass-1 compatible
- Internal AC coupling capacitors
- SYSREF Windowing for automatic SYSREF timing calibration
The DAC39RF10EF and RFS10EF are a family of dual and single channel digital-to-analog converters (DAC) with 16-bit resolution. The devices can be used as non-interpolating or interpolating DACs for either direct RF sampling or complex baseband signal generation. The maximum input data rate is 20.48GSPS for a single channel or 10.24GSPS for two channels. The device can generate signals of up to 10, 2.73 or 1GHz signal bandwidth (8, 11, and 16-bit input resolution) at carrier frequencies exceeding 8GHz enabling direct sampling through C-band and into X-band.
The high sampling rate, output frequency range, 64-bit NCO frequency resolution and any frequency hopping with phase coherence also makes DAC39RF10EF and RFS10EF capable of arbitrary waveform generation (AWG) and direct digital synthesis (DDS).
A JESD204B and JESD204C compatible serial interface has 16 receiver pairs capable of up to 12.8Gbps. The interface is JESD204B and JESD204C subclass-1 compliant for deterministic latency and multi-device synchronization through the use of SYSREF.
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
FCBGA (ACK) | 256 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點