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高速 SerDes
FPD-Link SerDes

DS90UH925Q-Q1

現行

具 HDCP 的 5 - 85 MHz 24 位元彩色 FPD-Link III 串聯器

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產品規格表

DS90UH925Q-Q1

現行
產品規格表 立即訂購

產品詳細資料

Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link III LVDS Color depth (bpp) 24 Features HDCP EMI reduction SSC Compatible Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link III LVDS Color depth (bpp) 24 Features HDCP EMI reduction SSC Compatible Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
WQFN (RHS) 48 49 mm² 7 x 7
  • Integrated HDCP Cipher Engine with On-chip Key
    Storage
  • Bidirectional Control Interface Channel Interface
    with I2C Compatible Serial Control Bus
  • Supports High Definition (720p) Digital Video
    Format
  • RGB888 + VS, HS, DE and I2S Audio Supported
  • 5 to 85 MHz PCLK Supported
  • Single 3.3V Operation with 1.8 V or 3.3 V Compatible
    LVCMOS I/O Interface
  • AC-coupled STP Interconnect up to 10 meters
  • Parallel LVCMOS Video Inputs
  • DC-balanced & Scrambled Data with Embedded
    Clock
  • HDCP Content Protected
  • Supports HDCP Repeater Application
  • Internal Pattern Generation
  • Low Power Modes Minimize Power Dissipation
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • > 8k V HBM and ISO 10605 ESD rating
  • Backward Compatible Modes
  • Integrated HDCP Cipher Engine with On-chip Key
    Storage
  • Bidirectional Control Interface Channel Interface
    with I2C Compatible Serial Control Bus
  • Supports High Definition (720p) Digital Video
    Format
  • RGB888 + VS, HS, DE and I2S Audio Supported
  • 5 to 85 MHz PCLK Supported
  • Single 3.3V Operation with 1.8 V or 3.3 V Compatible
    LVCMOS I/O Interface
  • AC-coupled STP Interconnect up to 10 meters
  • Parallel LVCMOS Video Inputs
  • DC-balanced & Scrambled Data with Embedded
    Clock
  • HDCP Content Protected
  • Supports HDCP Repeater Application
  • Internal Pattern Generation
  • Low Power Modes Minimize Power Dissipation
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • > 8k V HBM and ISO 10605 ESD rating
  • Backward Compatible Modes

The DS90UH925Q-Q1 serializer, in conjunction with the DS90UH926Q-Q1 deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission and full duplex control including I2C communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UH925Q-Q1 serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are serialized along with three video control signals and up to two I2S data inputs.

EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.

The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in on-chip memory.

The DS90UH925Q-Q1 serializer, in conjunction with the DS90UH926Q-Q1 deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission and full duplex control including I2C communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UH925Q-Q1 serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are serialized along with three video control signals and up to two I2S data inputs.

EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.

The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in on-chip memory.
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功能相同，但引腳輸出與所比較的裝置不同
DS90UH925AQ-Q1 現行 具有 HDCP 的 5 至 85 MHz 24 位元彩色 FPD-Link III 串聯器 Similar to DS90UH925Q-Q1 with addition of a local output pin for remote interrupt mirroring from deserializer

技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet DS90UH925Q-Q1 720p 24-bit Color FPD-Link III Serializer with HDCP datasheet (Rev. J) PDF | HTML 2014年 11月 7日
Application note Exploring the Int Test Pattern Generation Feature of FPD-Link III IVI Devices (Rev. G) PDF | HTML 2020年 11月 3日
Application note Enabling GPIOs in DS90UB925 and DS90UB926 2015年 11月 10日
Application note Using the I2S Audio Interface of DS90Ux92x FPD-Link III Devices 2013年 5月 4日
Application note I2C Communication Over FPD-Link III with Bidirectional Control Channel (Rev. A) 2013年 4月 26日
User guide DS90UH925QSEVB User's Guide 2012年 9月 20日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

DS90UH925QSEVB — DS90UH925QSEVB 評估板

The DS90UH925QSEVB is an evaluation board designed to demonstrate the performance and unique features of the DS90UH925Q FPD-Link III serializer.

The DS90UH925QSEVB board is designed to drive any of TI’s compatible FPD-Link III deserializer devices. The LVCMOS inputs of the DS90UH925Q are accessible (...)

使用指南: PDF
要求
應用軟體及架構

ALP — Analog LaunchPad Framework Utility

Analog LaunchPad (ALP) software is an interactive graphical user interface (GUI) software platform to evaluate TI FPD-Link™ serializers and deserializers (SerDes). ALP software enables device- and system-level evaluation with powerful built-in features, including:

  • Local and remote device access
  • (...)
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支援軟體

ALP-PROFILE-UPDATE — Analog LaunchPad Profile Update Software

Analog LaunchPad (ALP) software is an interactive graphical user interface (GUI) software platform to evaluate TI FPD-Link™ serializers and deserializers (SerDes). ALP software enables device- and system-level evaluation with powerful built-in features, including:

  • Local and remote device access
  • (...)
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模擬型號

DS90UH925Q IBIS Model

SNLM118.ZIP (67 KB) - IBIS Model
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
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模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
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參考設計

TIDA-00169 — 汽車 TFT LCD 顯示器解決方案

This reference design implements a video over LVDS solution for automotive infotainment applications.It highlights the support of multi-touch with haptic feedback, LCD backlight control, and ambient light sensing, without the introduction of dedicated support lines back to the host processor. This (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
WQFN (RHS) 48 Ultra Librarian
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