DS90UH927Q-Q1

現行

具 HDCP 的 5MHz - 85MHz 24 位元彩色 FPD-Link III 串聯器

產品詳細資料

Applications In-vehicle Infotainment (IVI) Input compatibility FPD-Link LVDS Function Serializer Output compatibility FPD-Link III LVDS Color depth (bpp) 24 Features HDCP Signal conditioning Adaptive Equalizer EMI reduction LVDS Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
Applications In-vehicle Infotainment (IVI) Input compatibility FPD-Link LVDS Function Serializer Output compatibility FPD-Link III LVDS Color depth (bpp) 24 Features HDCP Signal conditioning Adaptive Equalizer EMI reduction LVDS Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
WQFN (RTA) 40 36 mm² 6 x 6
  • Integrated HDCP Cipher Engine with On-Chip Key
    Storage
  • Bidirectional Control Channel Interface with I2C
    Compatible Serial Control Bus
  • Low EMI FPD-Link Video Input
  • Supports High Definition (720p) Digital Video
    Format
  • 5-MHz to 85-MHz PCLK Supported
  • RGB888 + VS, HS, DE and I2S Audio Supported
  • Up to 4 I2S Digital Audio Inputs for Surround
    Sound Applications
  • 4 Bidirectional GPIO Channels with 2 Dedicated
    Pins
  • Single 3.3-V Supply with 1.8-V or 3.3-V
    Compatible LVCMOS I/O Interface
  • AC-Coupled STP Interconnect up to 10 Meters
  • DC-Balanced & Scrambled Data with Embedded
    Clock
  • Supports HDCP Repeater Application
  • Internal Pattern Generation
  • Low Power Modes Minimize Power Dissipation
  • Automotive Grade Product: AEC-Q100 Grade 2
    Qualified
  • > 8-kV HBM and ISO 10605 ESD Rating
  • Backward Compatible Modes
  • Integrated HDCP Cipher Engine with On-Chip Key
    Storage
  • Bidirectional Control Channel Interface with I2C
    Compatible Serial Control Bus
  • Low EMI FPD-Link Video Input
  • Supports High Definition (720p) Digital Video
    Format
  • 5-MHz to 85-MHz PCLK Supported
  • RGB888 + VS, HS, DE and I2S Audio Supported
  • Up to 4 I2S Digital Audio Inputs for Surround
    Sound Applications
  • 4 Bidirectional GPIO Channels with 2 Dedicated
    Pins
  • Single 3.3-V Supply with 1.8-V or 3.3-V
    Compatible LVCMOS I/O Interface
  • AC-Coupled STP Interconnect up to 10 Meters
  • DC-Balanced & Scrambled Data with Embedded
    Clock
  • Supports HDCP Repeater Application
  • Internal Pattern Generation
  • Low Power Modes Minimize Power Dissipation
  • Automotive Grade Product: AEC-Q100 Grade 2
    Qualified
  • > 8-kV HBM and ISO 10605 ESD Rating
  • Backward Compatible Modes

The DS90UH927Q-Q1 serializer, in conjunction with a DS90UH928Q-Q1 or DS90UH926Q-Q1 deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a FPD-Link video interface into a single-pair high-speed serialized interface. The digital video data is protected using the industry standard High-Bandwidth Digital Content Protection (HDCP) copy protection scheme. The FPD-Link III serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed back channel communication over a single differential link. Consolidation of audio, video, and control data over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UH927Q-Q1 serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are serialized along with three video control signals, and up to four I2S data inputs.

The FPD-Link data interface allows for easy interfacing with data sources while also minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage differential signaling, data scrambling and randomization, and dc-balancing.

The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.

The DS90UH927Q-Q1 serializer, in conjunction with a DS90UH928Q-Q1 or DS90UH926Q-Q1 deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a FPD-Link video interface into a single-pair high-speed serialized interface. The digital video data is protected using the industry standard High-Bandwidth Digital Content Protection (HDCP) copy protection scheme. The FPD-Link III serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed back channel communication over a single differential link. Consolidation of audio, video, and control data over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UH927Q-Q1 serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are serialized along with three video control signals, and up to four I2S data inputs.

The FPD-Link data interface allows for easy interfacing with data sources while also minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage differential signaling, data scrambling and randomization, and dc-balancing.

The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.

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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet DS90UH927Q-Q1 5-MHz to 85-MHz 24-Bit Color FPD-Link III Serializer with HDCP datasheet (Rev. C) PDF | HTML 2015年 2月 2日
Application note Using the I2S Audio Interface of DS90Ux92x FPD-Link III Devices 2013年 5月 4日

設計與開發

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開發板

DS90UH927QEVM — DS90UH927Q-Q1 5 MHz-85 MHz FPD-Link III 串聯器評估模組

The Texas Instruments DS90UB927QEVM evaluation module (EVM) helps system designers evaluate the operation and performance of the DS90UB927Q 5MHz-85MHz FPD-Link III Serializer (SER). The device translates four FPD-Link (I) compatible LVDS data input pairs and one LVDS clock into a high-speed (...)

使用指南: PDF
應用軟體及架構

ALP Analog LaunchPad Framework Utility

Analog LaunchPad (ALP) software is an interactive graphical user interface (GUI) software platform to evaluate TI FPD-Link™ serializers and deserializers (SerDes). ALP software enables device- and system-level evaluation with powerful built-in features, including:

  • Local and remote device access
  • (...)
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支援產品和硬體

支援軟體

ALP-PROFILE-UPDATE Analog LaunchPad Profile Update Software

Analog LaunchPad (ALP) software is an interactive graphical user interface (GUI) software platform to evaluate TI FPD-Link™ serializers and deserializers (SerDes). ALP software enables device- and system-level evaluation with powerful built-in features, including:

  • Local and remote device access
  • (...)
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模擬型號

DS90UH927Q1 IBIS Model (Rev. A)

SNLM135A.ZIP (94 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一,涵蓋我們的類比和電源產品組合,以及特定類比行為模型,且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前,建立完整的終端設備設計和解決方案原型,進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中,您可以搜尋 TI (...)
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
WQFN (RTA) 40 Ultra Librarian

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  • 認證摘要
  • 進行中的可靠性監測
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