SN5472
- Packages Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages
- Dependable Texas Instruments Quality and Reliability
These J-K flip-flops are based on the master-slave principle and each has AND gate inputs for entry into the master section which are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows:
- 1. Isolate slave from master
- 2. Enter information from AND gate inputs to master
- 3. Disable AND gate inputs
- 4. Transfer information from master to slave
The logical states of the J and K inputs must not be allowed to change when the clock pulse is in a high state.
The SN5472, and the SN54H72 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7472 is characterized for operation from 0°C to 70°C.
您可能會感興趣的類似產品
功能與所比較的裝置相似
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 1 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | AND-Gated J-K Master-Slave Flip-Flops With Preset And Clear datasheet | 1988年 3月 1日 |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點