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邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型鎖存器

SN54ABT16373A

現行

具有 3 態輸出的 16 位元透明 D 型鎖存

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產品規格表

SN54ABT16373A

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 16 Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 89000 Features Flow-through pinout, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 16 Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 89000 Features Flow-through pinout, Partial power down (Ioff), Power up 3-state, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
CFP (WD) 48 153.4008 mm² 15.88 x 9.66
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

The 'ABT16373A are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16373A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16373A is characterized for operation from -40°C to 85°C.

The 'ABT16373A are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16373A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16373A is characterized for operation from -40°C to 85°C.

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類型 標題 日期
* Data sheet 16-Bit Transparent D-Type Latches With 3-State Outputs datasheet (Rev. C) 1997年 5月 1日
* SMD SN54ABT16373A SMD 5962-93200 2016年 6月 21日
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 2004年 2月 16日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
Selection guide Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 1997年 3月 1日
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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