SN54F109

Name: SN54F109
Brand: TI
SKU: SN54F109
Price: 7.562 USD

現行

具有清除和預設功能的雙路 J-K 正緣觸發正反器

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產品規格表

document-pdfAcrobat Dual J-K Positive-Edge-Triggered Flip-Flops w/Clear And Preset datasheet (Rev. A) (英文)

SN54F109

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

2

Technology family

F

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

IOL (max) (mA)

-1

IOH (max) (mA)

20

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

2

Technology family

F

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

IOL (max) (mA)

-1

IOH (max) (mA)

20

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

16

135.3552 mm² 19.56 x 6.92

CFP (W)

16

69.319 mm² 10.3 x 6.73

LCCC (FK)

20

79.0321 mm² 8.89 x 8.89

Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and trying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54F109 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C.

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and trying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54F109 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C.

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