產品詳細資料

Function Counter Bits (#) 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type 3-State Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Function Counter Bits (#) 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type 3-State Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • 8-Bit Counter with Register
  • Parallel Register Outputs
  • Choice of 3-State ('LS590) or Open-Collector ('LS591) Register Outputs
  • Guaranteed Counter Frequency:DC to 20 MHz

 

  • 8-Bit Counter with Register
  • Parallel Register Outputs
  • Choice of 3-State ('LS590) or Open-Collector ('LS591) Register Outputs
  • Guaranteed Counter Frequency:DC to 20 MHz

 

These devices each contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR\ and a count enable input CCKEN\. For cascading, a ripple carry output RCO\ is provided. Expansion is easily accomplished for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to CCK of the following stage.

Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable.

 

These devices each contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR\ and a count enable input CCKEN\. For cascading, a ripple carry output RCO\ is provided. Expansion is easily accomplished for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to CCK of the following stage.

Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable.

 

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類型 標題 日期
* Data sheet 8-Bit Binary Counters With Output Registers datasheet 1988年 3月 1日
* SMD SN54LS590 SMD 5962-87517 2016年 6月 21日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Designing with the SN54/74LS123 (Rev. A) 1997年 3月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
CDIP (J) 16 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

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