SN74AC563

Name: SN74AC563
Brand: TI
SKU: SN74AC563
Price: 0.574 USD

現行

具有 3 態輸出的八路 D 型透明鎖存器

立即訂購

產品規格表

document-pdfAcrobat SN54AC563, SN74AC563 datasheet (Rev. C) (英文)

SN74AC563

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

8

Technology family

AC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

80

Features

Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

AC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

80

Features

Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode

Operating temperature range (°C)

-40 to 85

Rating

Catalog

PDIP (N)

20

228.702 mm² 24.33 x 9.4

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SSOP (DB)

20

56.16 mm² 7.2 x 7.8

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

2-V to 6-V V_CC Operation
Inputs Accept Voltages to 6 V
Max t_pd of 9 ns at 5 V
3-State Inverting Outputs Drive Bus Lines Directly
Full Parallel Access for Loading
Flow-Through Architecture to Optimize PCB Layout

2-V to 6-V V_CC Operation
Inputs Accept Voltages to 6 V
Max t_pd of 9 ns at 5 V
3-State Inverting Outputs Drive Bus Lines Directly
Full Parallel Access for Loading
Flow-Through Architecture to Optimize PCB Layout

The ’AC563 devices are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

(OE)\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The ’AC563 devices are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

(OE)\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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