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D 型正反器

SN74ACT16374-EP

現行

具有 3 態輸出的增強型產品 16 位元 D 型邊緣觸發正反器

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產品規格表

SN74ACT16374-EP

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 16 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Schmitt-Trigger Output type Push-Pull Clock frequency (max) (MHz) 65 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 160 Features Balanced outputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating HiRel Enhanced Product
Number of channels 16 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Schmitt-Trigger Output type Push-Pull Clock frequency (max) (MHz) 65 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 160 Features Balanced outputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating HiRel Enhanced Product
SSOP (DL) 48 164.358 mm² 15.88 x 10.35
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree
  • Member of the Texas Instruments Widebus Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State Bus Driving True Outputs
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, highly accelerated stress test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life.
Widebus is a trademark of Texas Instruments.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –40°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product Change Notification
  • Qualification Pedigree
  • Member of the Texas Instruments Widebus Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State Bus Driving True Outputs
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, highly accelerated stress test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life.
Widebus is a trademark of Texas Instruments.

The SN74ACT16374Q-EP is a 16-bit edge-triggered D-type flip-flop with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

An output-enable (OE)\ input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system, without need for interface or pullup components. OE\ does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74ACT16374Q-EP is a 16-bit edge-triggered D-type flip-flop with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

An output-enable (OE)\ input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system, without need for interface or pullup components. OE\ does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
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類型 標題 日期
* Data sheet 16-Bit D-Type Edge-Triggered Flip-Flop With 3-State Outputs datasheet (Rev. B) 2002年 7月 11日
* Radiation & reliability report SN74ACT16374QDLREP Reliability Report (Rev. A) 2019年 9月 23日
* VID SN74ACT16374-EP VID V6203603 2016年 6月 21日
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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