SN74ACT563

Name: SN74ACT563
Brand: TI
SKU: SN74ACT563
Price: 0.331 USD

現行

具有 3 態輸出的八路 D 型透明鎖存器

立即訂購

產品規格表

document-pdfAcrobat SN54ACT563, SN74ACT563 datasheet (Rev. B) (英文)

SN74ACT563

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

8

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

90

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

40

Features

Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

90

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

40

Features

Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode

Operating temperature range (°C)

-40 to 85

Rating

Catalog

PDIP (N)

20

228.702 mm² 24.33 x 9.4

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

4.5-V to 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 8.5 ns at 5 V
Inputs Are TTL-Voltage Compatible
3-State Inverted Outputs Drive Bus Lines Directly
Flow-Through Architecture to Optimize PCB Layout

4.5-V to 5.5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 8.5 ns at 5 V
Inputs Are TTL-Voltage Compatible
3-State Inverted Outputs Drive Bus Lines Directly
Flow-Through Architecture to Optimize PCB Layout

The ’ACT563 devices are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputsare set to the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE)\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The ’ACT563 devices are octal D-type transparent latches with 3-state outputs. When the latch-enable (LE) input is high, the Q\ outputsare set to the complements of the data (D) inputs. When LE is taken low, the Q\ outputs are latched at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE)\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

filter

尋找其它 D 型鎖存器

下載